BE623642A - - Google Patents

Info

Publication number
BE623642A
BE623642A BE623642DA BE623642A BE 623642 A BE623642 A BE 623642A BE 623642D A BE623642D A BE 623642DA BE 623642 A BE623642 A BE 623642A
Authority
BE
Belgium
Application number
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Publication of BE623642A publication Critical patent/BE623642A/xx

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/50—Adding; Subtracting
    • G06F7/505—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2207/00—Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F2207/38—Indexing scheme relating to groups G06F7/38 - G06F7/575
    • G06F2207/3804—Details
    • G06F2207/386—Special constructional features
    • G06F2207/3876—Alternation of true and inverted stages

Landscapes

  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Pure & Applied Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computing Systems (AREA)
  • Mathematical Optimization (AREA)
  • General Engineering & Computer Science (AREA)
  • Complex Calculations (AREA)
  • Radar Systems Or Details Thereof (AREA)
BE623642D 1961-10-17 BE623642A (no)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US145594A US3249746A (en) 1961-10-17 1961-10-17 Data processing apparatus

Publications (1)

Publication Number Publication Date
BE623642A true BE623642A (no)

Family

ID=22513783

Family Applications (1)

Application Number Title Priority Date Filing Date
BE623642D BE623642A (no) 1961-10-17

Country Status (6)

Country Link
US (1) US3249746A (no)
BE (1) BE623642A (no)
DE (1) DE1241159B (no)
GB (1) GB981922A (no)
NL (1) NL284402A (no)
SE (1) SE307685B (no)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB1088354A (en) * 1965-06-01 1967-10-25 Int Computers & Tabulators Ltd Improvements in or relating to electronic adders
US3375358A (en) * 1965-08-30 1968-03-26 Fabri Tek Inc Binary arithmetic network
US3465133A (en) * 1966-06-07 1969-09-02 North American Rockwell Carry or borrow system for arithmetic computations
US3506817A (en) * 1967-02-24 1970-04-14 Rca Corp Binary arithmetic circuits employing threshold gates in which both the sum and carry are obtained in one gate delay interval
DE2647262A1 (de) * 1975-11-04 1977-05-05 Motorola Inc Multiplizierschaltung
US4052604A (en) * 1976-01-19 1977-10-04 Hewlett-Packard Company Binary adder
US4766565A (en) * 1986-11-14 1988-08-23 International Business Machines Corporation Arithmetic logic circuit having a carry generator
US4768161A (en) * 1986-11-14 1988-08-30 International Business Machines Corporation Digital binary array multipliers using inverting full adders

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB840545A (en) * 1955-06-02 1960-07-06 Kokusai Denshin Denwa Co Ltd Electric borrowing circuit suitable for use in a binary subtractive circuit
US2879001A (en) * 1956-09-10 1959-03-24 Weinberger Arnold High-speed binary adder having simultaneous carry generation

Also Published As

Publication number Publication date
US3249746A (en) 1966-05-03
DE1241159B (de) 1967-05-24
GB981922A (en) 1965-01-27
NL284402A (no)
SE307685B (no) 1969-01-13

Similar Documents

Publication Publication Date Title
BE624137A (no)
BE164003A (no)
BE396226A (no)
BE458606A (no)
BE464928A (no)
BE469342A (no)
BE472265A (no)
BE475425A (no)
BE475477A (no)
BE476407A (no)
BE478349A (no)
BE482264A (no)
BE493336A (no)
BE567723A (no)
BE568568A (no)
BE583834A (no)
BE587184A (no)
BE596839A (no)
BE597352A (no)
BE597570A (no)
BE598861A (no)
BE599016A (no)
BE599210A (no)
BE599528A (no)
BE599922A (no)