SE307685B - - Google Patents
Info
- Publication number
- SE307685B SE307685B SE11143/62A SE1114362A SE307685B SE 307685 B SE307685 B SE 307685B SE 11143/62 A SE11143/62 A SE 11143/62A SE 1114362 A SE1114362 A SE 1114362A SE 307685 B SE307685 B SE 307685B
- Authority
- SE
- Sweden
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
- G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
- G06F7/50—Adding; Subtracting
- G06F7/505—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2207/00—Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F2207/38—Indexing scheme relating to groups G06F7/38 - G06F7/575
- G06F2207/3804—Details
- G06F2207/386—Special constructional features
- G06F2207/3876—Alternation of true and inverted stages
Landscapes
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computational Mathematics (AREA)
- Mathematical Analysis (AREA)
- Pure & Applied Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Computing Systems (AREA)
- Mathematical Optimization (AREA)
- General Engineering & Computer Science (AREA)
- Complex Calculations (AREA)
- Radar Systems Or Details Thereof (AREA)
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US145594A US3249746A (en) | 1961-10-17 | 1961-10-17 | Data processing apparatus |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| SE307685B true SE307685B (xx) | 1969-01-13 |
Family
ID=22513783
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| SE11143/62A SE307685B (xx) | 1961-10-17 | 1962-10-17 |
Country Status (6)
| Country | Link |
|---|---|
| US (1) | US3249746A (xx) |
| BE (1) | BE623642A (xx) |
| DE (1) | DE1241159B (xx) |
| GB (1) | GB981922A (xx) |
| NL (1) | NL284402A (xx) |
| SE (1) | SE307685B (xx) |
Families Citing this family (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB1088354A (en) * | 1965-06-01 | 1967-10-25 | Int Computers & Tabulators Ltd | Improvements in or relating to electronic adders |
| US3375358A (en) * | 1965-08-30 | 1968-03-26 | Fabri Tek Inc | Binary arithmetic network |
| US3465133A (en) * | 1966-06-07 | 1969-09-02 | North American Rockwell | Carry or borrow system for arithmetic computations |
| US3506817A (en) * | 1967-02-24 | 1970-04-14 | Rca Corp | Binary arithmetic circuits employing threshold gates in which both the sum and carry are obtained in one gate delay interval |
| DE2647262A1 (de) * | 1975-11-04 | 1977-05-05 | Motorola Inc | Multiplizierschaltung |
| US4052604A (en) * | 1976-01-19 | 1977-10-04 | Hewlett-Packard Company | Binary adder |
| US4766565A (en) * | 1986-11-14 | 1988-08-23 | International Business Machines Corporation | Arithmetic logic circuit having a carry generator |
| US4768161A (en) * | 1986-11-14 | 1988-08-30 | International Business Machines Corporation | Digital binary array multipliers using inverting full adders |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB840545A (en) * | 1955-06-02 | 1960-07-06 | Kokusai Denshin Denwa Co Ltd | Electric borrowing circuit suitable for use in a binary subtractive circuit |
| US2879001A (en) * | 1956-09-10 | 1959-03-24 | Weinberger Arnold | High-speed binary adder having simultaneous carry generation |
-
0
- BE BE623642D patent/BE623642A/xx unknown
- NL NL284402D patent/NL284402A/xx unknown
-
1961
- 1961-10-17 US US145594A patent/US3249746A/en not_active Expired - Lifetime
-
1962
- 1962-09-24 GB GB36293/62A patent/GB981922A/en not_active Expired
- 1962-10-16 DE DER33695A patent/DE1241159B/de active Pending
- 1962-10-17 SE SE11143/62A patent/SE307685B/xx unknown
Also Published As
| Publication number | Publication date |
|---|---|
| US3249746A (en) | 1966-05-03 |
| DE1241159B (de) | 1967-05-24 |
| NL284402A (xx) | |
| GB981922A (en) | 1965-01-27 |
| BE623642A (xx) |