AU7693198A - Processor interfacing to memory-centric computing engine - Google Patents

Processor interfacing to memory-centric computing engine

Info

Publication number
AU7693198A
AU7693198A AU76931/98A AU7693198A AU7693198A AU 7693198 A AU7693198 A AU 7693198A AU 76931/98 A AU76931/98 A AU 76931/98A AU 7693198 A AU7693198 A AU 7693198A AU 7693198 A AU7693198 A AU 7693198A
Authority
AU
Australia
Prior art keywords
memory
computing engine
centric computing
processor interfacing
interfacing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
AU76931/98A
Inventor
Richard Rubinstein
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Individual
Original Assignee
Individual
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US08/869,148 external-priority patent/US6691206B1/en
Application filed by Individual filed Critical Individual
Publication of AU7693198A publication Critical patent/AU7693198A/en
Abandoned legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3885—Concurrent instruction execution, e.g. pipeline, look ahead using a plurality of independent parallel functional units
    • G06F9/3893—Concurrent instruction execution, e.g. pipeline, look ahead using a plurality of independent parallel functional units controlled in tandem, e.g. multiplier-accumulator
    • G06F9/3895—Concurrent instruction execution, e.g. pipeline, look ahead using a plurality of independent parallel functional units controlled in tandem, e.g. multiplier-accumulator for complex operations, e.g. multidimensional or interleaved address generators, macros
    • G06F9/3897—Concurrent instruction execution, e.g. pipeline, look ahead using a plurality of independent parallel functional units controlled in tandem, e.g. multiplier-accumulator for complex operations, e.g. multidimensional or interleaved address generators, macros with adaptable data path
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3877—Concurrent instruction execution, e.g. pipeline, look ahead using a slave processor, e.g. coprocessor
    • G06F9/3879—Concurrent instruction execution, e.g. pipeline, look ahead using a slave processor, e.g. coprocessor for non-native instruction execution, e.g. executing a command; for Java instruction set
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/42—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation
    • H04N19/423—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation characterised by memory arrangements
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/60—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using transform coding
    • H04N19/61—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using transform coding in combination with predictive coding
AU76931/98A 1997-06-04 1998-05-22 Processor interfacing to memory-centric computing engine Abandoned AU7693198A (en)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US86927797A 1997-06-04 1997-06-04
US08/869,148 US6691206B1 (en) 1997-03-21 1997-06-04 Processor interfacing to memory-centric computing engine
US08869148 1997-06-04
US08869277 1997-06-04
PCT/US1998/010549 WO1998055932A2 (en) 1997-06-04 1998-05-22 Processor interfacing to memory mapped computing engine

Publications (1)

Publication Number Publication Date
AU7693198A true AU7693198A (en) 1998-12-21

Family

ID=27128095

Family Applications (1)

Application Number Title Priority Date Filing Date
AU76931/98A Abandoned AU7693198A (en) 1997-06-04 1998-05-22 Processor interfacing to memory-centric computing engine

Country Status (3)

Country Link
EP (1) EP0986787A2 (en)
AU (1) AU7693198A (en)
WO (1) WO1998055932A2 (en)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE10003006A1 (en) * 2000-01-25 2001-07-26 Bosch Gmbh Robert Arrangement and method for signal processing and storage
US6643800B1 (en) * 2000-02-02 2003-11-04 Hewlett-Packard Development Company, L.P. Method and apparatus for testing microarchitectural features by using tests written in microcode
WO2002093508A1 (en) * 2001-05-16 2002-11-21 Georges Chiche Portable personal medical file system
US7971030B2 (en) 2002-08-07 2011-06-28 Mmagix Technology Limited Method for using multiple processing resources which share multiple co-processor resources
US20060176955A1 (en) * 2005-02-07 2006-08-10 Lu Paul Y Method and system for video compression and decompression (codec) in a microprocessor

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58144272A (en) * 1982-02-19 1983-08-27 Sony Corp Digital signal processor
JPS6097458A (en) * 1983-10-18 1985-05-31 インタ−ナショナル　ビジネス　マシ−ンズ　コ−ポレ−ション Data transfer unit
US5230042A (en) * 1987-09-25 1993-07-20 Minolta Camera Kabushiki Kaisha Digital image processing apparatus
US4862407A (en) * 1987-10-05 1989-08-29 Motorola, Inc. Digital signal processing apparatus
JPH04255989A (en) * 1991-02-07 1992-09-10 Mitsubishi Electric Corp Semiconductor memory
US5448715A (en) * 1992-07-29 1995-09-05 Hewlett-Packard Company Dual clock domain interface between CPU and memory bus
US5396634A (en) * 1992-09-30 1995-03-07 Intel Corporation Method and apparatus for increasing the decoding speed of a microprocessor
WO1994012929A1 (en) * 1992-11-23 1994-06-09 Seiko Epson Corporation A microcode cache system and method
JPH07130166A (en) * 1993-09-13 1995-05-19 Mitsubishi Electric Corp Semiconductor storage device and synchronization type semiconductor storage device
JP3780011B2 (en) * 1995-07-14 2006-05-31 株式会社ルネサステクノロジ Semiconductor memory device

Also Published As

Publication number Publication date
EP0986787A2 (en) 2000-03-22
WO1998055932A3 (en) 1999-08-12
WO1998055932A2 (en) 1998-12-10

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Legal Events

Date Code Title Description
MK6 Application lapsed section 142(2)(f)/reg. 8.3(3) - pct applic. not entering national phase