WO1998055932A3 - Processor interfacing to memory mapped computing engine - Google Patents
Processor interfacing to memory mapped computing engineInfo
- Publication number
- WO1998055932A3 WO1998055932A3 PCT/US1998/010549 US9810549W WO1998055932A3 WO 1998055932 A3 WO1998055932 A3 WO 1998055932A3 US 9810549 W US9810549 W US 9810549W WO 1998055932 A3 WO1998055932 A3 WO 1998055932A3
- Authority
- WO
- Grant status
- Application
- Patent type
- Prior art keywords
- processing
- series
- microcode
- memory
- engine
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for programme control, e.g. control unit
- G06F9/06—Arrangements for programme control, e.g. control unit using stored programme, i.e. using internal store of processing equipment to receive and retain programme
- G06F9/30—Arrangements for executing machine-instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
- G06F9/3885—Concurrent instruction execution, e.g. pipeline, look ahead using a plurality of independent parallel functional units
- G06F9/3893—Concurrent instruction execution, e.g. pipeline, look ahead using a plurality of independent parallel functional units controlled in tandem, e.g. multiplier-accumulator
- G06F9/3895—Concurrent instruction execution, e.g. pipeline, look ahead using a plurality of independent parallel functional units controlled in tandem, e.g. multiplier-accumulator for complex operations, e.g. multidimensional or interleaved address generators, macros
- G06F9/3897—Concurrent instruction execution, e.g. pipeline, look ahead using a plurality of independent parallel functional units controlled in tandem, e.g. multiplier-accumulator for complex operations, e.g. multidimensional or interleaved address generators, macros with adaptable data path
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for programme control, e.g. control unit
- G06F9/06—Arrangements for programme control, e.g. control unit using stored programme, i.e. using internal store of processing equipment to receive and retain programme
- G06F9/30—Arrangements for executing machine-instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
- G06F9/3877—Concurrent instruction execution, e.g. pipeline, look ahead using a slave processor, e.g. coprocessor
- G06F9/3879—Concurrent instruction execution, e.g. pipeline, look ahead using a slave processor, e.g. coprocessor for non-native instruction execution, e.g. executing a command; for Java instruction set
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
- H04N19/42—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation
- H04N19/423—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation characterised by memory arrangements
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
- H04N19/60—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using transform coding
- H04N19/61—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using transform coding in combination with predictive coding
Abstract
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US08/869,148 | 1997-06-04 | ||
US08/869,277 | 1997-06-04 | ||
US08869148 US6691206B1 (en) | 1997-03-21 | 1997-06-04 | Processor interfacing to memory-centric computing engine |
US86927797 true | 1997-06-21 | 1997-06-21 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP19980924857 EP0986787A2 (en) | 1997-06-04 | 1998-05-22 | Processor interfacing to memory mapped computing engine |
Publications (2)
Publication Number | Publication Date |
---|---|
WO1998055932A2 true WO1998055932A2 (en) | 1998-12-10 |
WO1998055932A3 true true WO1998055932A3 (en) | 1999-08-12 |
Family
ID=27128095
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/US1998/010549 WO1998055932A3 (en) | 1997-03-21 | 1998-05-22 | Processor interfacing to memory mapped computing engine |
Country Status (2)
Country | Link |
---|---|
EP (1) | EP0986787A2 (en) |
WO (1) | WO1998055932A3 (en) |
Families Citing this family (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE10003006A1 (en) * | 2000-01-25 | 2001-07-26 | Bosch Gmbh Robert | Arrangement and method for signal processing and storing |
US6643800B1 (en) * | 2000-02-02 | 2003-11-04 | Hewlett-Packard Development Company, L.P. | Method and apparatus for testing microarchitectural features by using tests written in microcode |
WO2002093508A1 (en) * | 2001-05-16 | 2002-11-21 | Georges Chiche | Portable personal medical file system |
WO2004015572A1 (en) | 2002-08-07 | 2004-02-19 | Mmagix Technology Limited | Apparatus, method and system for a synchronicity independent, resource delegating, power and instruction optimizing processor |
US20060176955A1 (en) * | 2005-02-07 | 2006-08-10 | Lu Paul Y | Method and system for video compression and decompression (codec) in a microprocessor |
Citations (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0139254A2 (en) * | 1983-10-18 | 1985-05-02 | International Business Machines Corporation | Apparatus and method for direct memory to peripheral and peripheral to memory data transfer |
GB2155671A (en) * | 1982-02-19 | 1985-09-25 | Sony Corp | Digital signal processing systems |
US4862407A (en) * | 1987-10-05 | 1989-08-29 | Motorola, Inc. | Digital signal processing apparatus |
EP0498107A2 (en) * | 1991-02-07 | 1992-08-12 | Mitsubishi Denki Kabushiki Kaisha | A semiconductor memory device with an internal voltage generating circuit |
US5230042A (en) * | 1987-09-25 | 1993-07-20 | Minolta Camera Kabushiki Kaisha | Digital image processing apparatus |
WO1994012929A1 (en) * | 1992-11-23 | 1994-06-09 | Seiko Epson Corporation | A microcode cache system and method |
US5396634A (en) * | 1992-09-30 | 1995-03-07 | Intel Corporation | Method and apparatus for increasing the decoding speed of a microprocessor |
DE4432217A1 (en) * | 1993-09-13 | 1995-03-16 | Mitsubishi Electric Corp | Clock-synchronous semiconductor memory device |
US5448715A (en) * | 1992-07-29 | 1995-09-05 | Hewlett-Packard Company | Dual clock domain interface between CPU and memory bus |
JPH0934783A (en) * | 1995-07-14 | 1997-02-07 | Mitsubishi Electric Corp | A semiconductor memory device |
Patent Citations (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
GB2155671A (en) * | 1982-02-19 | 1985-09-25 | Sony Corp | Digital signal processing systems |
EP0139254A2 (en) * | 1983-10-18 | 1985-05-02 | International Business Machines Corporation | Apparatus and method for direct memory to peripheral and peripheral to memory data transfer |
US5230042A (en) * | 1987-09-25 | 1993-07-20 | Minolta Camera Kabushiki Kaisha | Digital image processing apparatus |
US4862407A (en) * | 1987-10-05 | 1989-08-29 | Motorola, Inc. | Digital signal processing apparatus |
EP0498107A2 (en) * | 1991-02-07 | 1992-08-12 | Mitsubishi Denki Kabushiki Kaisha | A semiconductor memory device with an internal voltage generating circuit |
US5448715A (en) * | 1992-07-29 | 1995-09-05 | Hewlett-Packard Company | Dual clock domain interface between CPU and memory bus |
US5396634A (en) * | 1992-09-30 | 1995-03-07 | Intel Corporation | Method and apparatus for increasing the decoding speed of a microprocessor |
WO1994012929A1 (en) * | 1992-11-23 | 1994-06-09 | Seiko Epson Corporation | A microcode cache system and method |
DE4432217A1 (en) * | 1993-09-13 | 1995-03-16 | Mitsubishi Electric Corp | Clock-synchronous semiconductor memory device |
JPH0934783A (en) * | 1995-07-14 | 1997-02-07 | Mitsubishi Electric Corp | A semiconductor memory device |
US5726947A (en) * | 1995-07-14 | 1998-03-10 | Mitsubishi Denki Kabushiki Kaisha | Synchronous semiconductor memory device suitable for graphic data processing |
Non-Patent Citations (3)
Title |
---|
A. C. DAVIES ET AL.: "Interfacing a Hardware Multiplier to a General-purpose Microprocessor", MICROPROCESSORS AND MICROSYSTEMS., vol. 1, no. 7, October 1977 (1977-10-01), LONDON GB, pages 425 - 431, XP000212024 * |
ERTEM M C: "A RECONFIGURABLE CO-PROCESSOR FOR MICROPROCESSOR SYSTEMS", PROCEEDINGS OF THE SOUTHEAST CONFERENCE, TAMPA, APRIL 5 - 8, 1987, vol. 1, 5 April 1987 (1987-04-05), INSTITUTE OF ELECTRICAL AND ELECTRONICS ENGINEERS, pages 225 - 228, XP000212298 * |
PATENT ABSTRACTS OF JAPAN vol. 097, no. 006 30 June 1997 (1997-06-30) * |
Also Published As
Publication number | Publication date | Type |
---|---|---|
WO1998055932A2 (en) | 1998-12-10 | application |
EP0986787A2 (en) | 2000-03-22 | application |
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