AU730334B2 - Harmonic compensation apparatus and methods - Google Patents

Description

WO 98/57408 PCT/NZ98/00084 "HARMONIC COMPENSATION APPARATUS AND METHODS" FIELD OF THE INVENTION This invention relates to harmonic compensation apparatus or methods and/or control methods for harmonic compensation apparatus.

BACKGROUND TO THE INVENTION Many loads in electric power distribution systems draw harmonic currents. These have a significant detrimental affect onthe quality of the power delivered by the system. In particular, harmonics lead to inefficiencies, place greater stresses on system components and can cause interference with and improper operation of electrical equipment.

Although active filter systems have been proposed, they suffer disadvantages including low efficiency, poor transient performance and limited capabilities.

Known harmonic compensation apparatus use inverter structures that operate from a single DC bus, for example 565 700 V DC. For a three phase power distribution system a single bus necessitates at least 6 switches. With only a six switch, three phase, three wire inverter structure, harmonic triplens cannot be compensated.

Furthermore, the control strategies used with these known constructions in many cases refer to the last cycle of the mains power supply to determine the correction or compensation to be applied to the current cycle. Therefore, their response to transient load changes is poor. Pulse Width Modulation (PWM) is a commonly used control method for inverter structures. The method usually compares the inverter output current with a desired current level (corresponding to an output which will substantially eliminate harmonics on the line) to provide a reference level which is used to determine the PWM duty cycle for switch control. The basic problem with this approach is that the speed of the comparator output must be limited. This delay results in poor transient performance. Also, if the speed of response of the comparator is increased significantly the risk of unstable oscillation also increases.

WO 98/57408 PCT/NZ98/00084 Existing constructions also have significant problems compensating harmonics in polyphase systems that have a neutral line.

SUMMARY OF THE INVENTION It is an object of the invention to provide harmonic compensation apparatus or methods and/or control methods for harmonic compensation apparatus which will at least go some way toward overcoming the foregoing disadvantages, or which will at least provide the public with a useful choice.

In one aspect the invention may broadly be said to consist in harmonic compensation apparatus to remove at least one harmonic component from an alternating current power distribution system, the power distribution system having a line current waveform including a fundamental and at least one harmonic frequency component flowing through a line connected to a load, the apparatus including; control signal generating means for producing a control signal corresponding to a line current or line voltage waveform substantially devoid of the at least one harmonic component and establishing predetermined boundaries relative to the control signal, the predetermined boundaries corresponding to desired boundaries for a line current or a line voltage substantially devoid of the at least one harmonic component, switching means for supplying or drawing current to or from the line, and switching control means to control the switching means to supply or draw current to or from the line to create a line current or line voltage which is within the desired boundaries and which is substantially devoid of the at least one harmonic component.

In a further aspect the invention may broadly be said to consist in harmonic compensation apparatus to remove at least one harmonic component from an alternating current power distribution system, the power distribution system having a current waveform including a fundamental and at least one harmonic frequency component flowing through a line connected to a load, the apparatus including; a first controllable switching means for increasing or reducing current in the line in a positive half voltage cycle of the system, a second controllable switching means for increasing or reducing the line current in a negative half voltage cycle, a third controllable switching means for increasing or reducing line current in both the positive and negative half voltage cycles, and WO 98/57408 PCT/NZ98/00084 control means for controlling the switching means to cormipensate for the at least one harmonic component.

In a further aspect the invention may broadly be said to consist in harmonic compensation apparatus to remove at least one harmonic component from an alternating current power distribution system, the power distribution system having a current waveform including a fundamental and at least one harmonic frequency component flowing through a line connected to a load, the apparatus including; control signal generating means for producing a control signal corresponding to a line current or line voltage waveform substantially devoid of significant harmonics and establishing predetermined boundaries relative to the control signal, switching means for supplying or drawing current to or from the line, and switching control means to control the switching means to supply or draw current to or from the line to create a line current or line voltage which is within the predetermined boundaries.

In a further aspect the invention may broadly be said to consist in a method of compensating for at least one harmonic component from an alternating current power distribution system, the power distribution system having a current waveform including a fundamental and at least one harmonic frequency component flowing through a line connected to a load, the method comprising the steps of; producing a control signal corresponding to a desired line current or line voltage waveform which is substantially devoid of the at least one harmonic component, establishing predetermined boundaries relative to the control signal, the predetermined boundaries corresponding to desired boundaries for a line current or a line voltage substantially devoid of the at least one harmonic component, and supplying or drawing current to or from the line to create a line current or line voltage which is within the desired boundaries and which is substantially devoid of the at least one harmonic component.

The invention may also broadly be said to consist in the parts, elements and features referred to or indicated in the specification of the application, individually or collectively, and any or all combinations of any two or more of the said parts, elements or features, and where elements or features are mentioned herein and which have known WO 98/57408 PCTINZ98/00084 equivalents in the art to which this invention relates, such known equivalents are deemed to be incorporated herein as if individually set forth.

To those skilled in the art to which the invention relates, many changes in construction and widely differing embodiments and applications of the invention will suggest themselves without departing from the scope of the invention as defined in the appended claims. The disclosures and the descriptions herein are purely illustrative and are not intended to be in any sense limiting.

The invention consists of the foregoing and also envisages constructions of which the following gives examples.

BRIEF DESCRIPTION OF THE DRAWINGS One preferred form of the present invention will now be described with reference to the accompanying drawings in which; Figure 1 is a simplified schematic circuit diagram of apparatus in accordance with the present invention.

Figure 2 is a schematic diagram of a harmonic control circuit included in figure 1.

Figure 3 is a schematic diagram of a bus regulator control circuit included in figure 1.

Figure 4 is a schematic diagram of a further part of the bus regulator circuit of figure 3.

Figure 5 is a flow chart showing operation of a further part of the circuit referred to in figures 3 and 4.

Figure 6 is a diagrammatic graph of a current wave form of current plotted on the vertical axis against time on the horizontal axis.

WO 98/57408 PCT/NZ98/00084 Figure 7 is a partial schematic circuit diagram of switchinfig control circuitry in accordance with the present invention.

Figure 8 is a partial schematic circuit diagram of further control circuitry and continues from the circuitry shown in figure 7.

Figure 9 is a circuit diagram in schematic form of power stage switching apparatus in accordance with the present invention.

Figure 10 is a simplified circuit diagram showing combined outputs of two of the power stages of the-present invention.

Figure 11 is a circuit diagram illustrating a model of the operation of the switching circuitry referred to in figure 9.

Figure 12 is two graphs of current plotted on the vertical axis against time on the horizontal axis relating to the model shown in figure 11, and Figure 13 is a circuit diagram of a three-level bridge in accordance with the present invention.

DETAILED DESCRIPTION OF A PREFERRED EMBODIMENT Referring to Figure 1, apparatus comprising an active harmonic compensator ("AHC") is shown in schematic form. The AHC apparatus is in use connected in parallel (at connection points 2 in figure 1) to a load RL which draws harmonics, for example a personal computer. The load is connected across a mains power supply M. In Figure 1, for the purposes of explanation, a portion of the AHC used to provide harmonic compensation for only one phase is shown. By replicating the apparatus of figure 1, an AHC capable of providing harmonic compensation for a 3 phase system or polyphase system is provided. The AHC apparatus will usually be used on a three phase or polyphase system.

Quite apart from the parallel connection at connection points 2 to the load RL, the AHC includes a current sensing device comprising a standard current transformer3 which is in use connected so as sense current being drawn by tbaJoadand the AHC. The WO 98/57408 PCT/NZ98/00084 signal that the current transformer 3 and associated signal amplifier 4 provides is indicative of the current in the load and AHC, is supplied to the harmonic control section. A shunt 5 provides a signal indicative of the current being drawn from or supplied to the line by the AHC. For the purposes of ease of explanation of the invention the schematic diagram of Figure 1 has been divided into general sections. It will be seen that apart from the harmonic control section 6, there is a bus regulator section 8, a switching control section 10, a gate drive section 12, a power stage or inverter section 14 and a protection section 18.

The AHC apparatus will now be described with reference to the above sections.

Harmonic Control Section Referring to Figure 2, the harmonic control section 6 is provided with a signal indicative of the line current drawn by the load and AHC apparatus from current transformer 3 (Figure 1) which is referred to in Figure 2 as "I LINE". The current drawn or supplied by the AHC is sensed by shunt 5. The amplified signal output of the current transformer 3 and the shunt 5 are fed to subtractor 20, the output 22 of which represents the load current I LOAD, being the difference between I LINE and the current drawn or supplied by the AHC. It will be seen that this method of current derivation allows the load current, for example, to be sensed and, knowing the AHC current from shunt 5, allows I LINE to be derived by algebraic addition, where the current transformer is placed to measure load current only.

The signal representative of I LOAD at output 22 is fed to generation means comprising a phase locked loop 62 which generates a sinusoidal signal at output 24 which is in phase with the fundamental component of the load current I LOAD. The approximate frequency range of the sinusoid generated is 45-65Hz. The sinusoid generated is referenced "I SINE" in Figure 2 and this passes through a controlled resistor 64 to be summed with I LOAD after it has passed through resistor 66, the output appearing at node 68. The output of the summing circuitry produces an output signal "1 SIG" which is a composite of I LOAD and I SINE.

The controlled resistor 64 is very high impedance at start up of the AHC apparatus, so that the power stage 14 does not inject or draw current to or from the mains supply to WO 98/57408 PCT/NZ98/00084 correct for harmonics other than to draw a slight amount of real power (as described further below). The impedance of controlled resistor 64 is slowly decreased during start up so that harmonics are initially gradually compensated. This avoids sudden transients occurring before the capacitor bus voltages 15 have stabilised.

As the start up of the AHC apparatus proceeds, the controlled resistor 64 has its impedance gradually reduced so that the I SIG output becomes more sinusoidal in shape to cause the power stage 14 to inject or draw current to or from the mains so as to compensate. for and thus correct harmonics in the system and thereby substantially achieve a sine wave from current transformer 3 so that I LINE is substantially representative of a sine wave.

The controlled resistor 64 provides a form of control for the apparatus in that when the power stage 14 is nearing its RMS current limit, the value of the controlled resistor 64 is increased. In this way there is a reduced influence of I SINE on I SIG, so that the power stage 14 draws or injects less current, i.e. it does less harmonic correction.

Similarly, for over temperature or stop, reset or over voltage conditions, the controlled resistor 64 has its impedance increased when these conditions occur. The sensing circuitry for these overload conditions is provided by protection section 18.

Although the circuitry described with reference to the harmonic control section does not provide an indication of the phase difference between the mains voltage V LINE and I LINE, it will be seen from the foregoing description that such an indication could easily be provided. In this way the apparatus of the present invention could provide power factor correction by shifting I LINE to be more in phase with the mains voltage V LINE. This would be achieved by replacing I SINE with V SINE V SINE being a signal derived by resistive divider from the phase voltage.

Bus Regulator Section Referring to Figure 3, a part of the circuitry included in the bus regulator section is shown for providing an indication as to the DC voltage on the DC buses supplied by the capacitor banks 15 of the power stage. Referring to Figure 3, the banks 15 are shown connected to a differential amplifier generally referenced 82 the output of which WO 98/57408 PCT/NZ98/00084 is supplied to a comparator 84 which has a deliberately biesigned slow (for example several milliseconds response time) response so as to effectively act as a low pass filter and therefore look at time averaged voltages from the DC buses. The output of the comparator is provided to an inversion amplifier 86. Thus the output of the inversion amplifier increases when the DC bus voltages drop below a certain predetermined value and decreases when the DC bus voltages increase above a predetermined value (for example, 820 volts average).

Still referring to figure 3, amplifiers 70 and 72 form the basis of speed up circuits to provide a faster response to changes in the bus voltages. Amplifier 70.and associated components provide a faster response to overvoltage conditions on the bus. Thus the bus voltage signal is fed to the inverting input of amplifier 70. If there is an overvoltage condition, then the output of this amplifier which is normally high will go low, which will forward bias diode 74. This will cause the output of amplifier 84 to go high, so inverter 86 will decrease the bus error signal to decrease the bus voltage. Conversely, if there is an undervoltage condition, then the normally low output of amplifier 72 will go high to forward bias diode 76. This will cause the output of amplifier 84 to go low, so inverter 86 will increase the bus error signal.

Turning to Figure 4, I SIG of node 68 is added to a variable (but very small) amount of V LINE. The output of the inversion amplifier 86 is multiplied by a multiplier 88 with the modified I SIG signal the mixed I SINE, I LOAD signals and a proportion of V LINE) from the harmonic control section 6 (refer Figure The output from the multiplier is supplied to the non inverting input of amplifier 89. This amplifier is configured to do the following: amplify the signal at the non inverting input, and incorporate an offset generated by a filter 85 which filter is fed from the current obtained from shunt 5 (figure The purpose of the offset, as described further below, is to counteract any tendency of the AHC to draw a DC current. The output of amplifier 89 is referenced I REF. I REF is supplied to the switching control section 10 as will be described further below.

The significance of the I REF signal in relation to the control strategy is that: 1. If the magnitude of I REF is too small, the power stage 14 exports power to the load RL and the mains M which will reduce I LINE. This will cause the DC WO 98/57408 PCT/NZ98/00084 buses to discharge and lower their voltage. This-reduction in voltage will result in the output of inversion amplifier 86 going high which will cause multiplier 88 to pass through a greater proportion of the I SIG input from the harmonic controlsection 6. This will increase I REF until an equilibrium is reached.

The form of I REF provides the desired waveform that is substantially free of harmonics. The AHC attempts to force the line current I LINE to conform to the form of I REF.

The response of the control circuitry to transient load changes is improved considerably by using error amplifiers 70 and 72 so that if a transient change in load occurs causing the voltage on the capacitor banks 15 to move close to their operational limits (eg. 380 V or 440 V DC), then the speed up circuits can make a quick coarse correction to comparator 84 so that the output of comparator 84 will reach its new equilibrium state faster. The control strategy embodied in this section (and the other control sections) could be implemented using digital control methods and circuitry including processor means such as a microprocessor.

When the fundamental component of I LOAD is well phased displaced (eg. 60 degrees lagging behind the phase voltage), I REF needs to contain some in-phase (with V LINE) component so that the AHC will draw real power to keep the buses at the required DC voltage levels and to overcome losses in the circuit. The amount of real power needed depends on how hard the inverter is working as losses increase with current. Ideally the amount of real power required can be calculated and this figure then used to select the amount of in-phase signal to add to the control signal to obtain the correct I REF control signal.

In practice, we have found that the rather difficult calculation referred to in the preceding paragraph can be avoided by simply varying the amount of in-phase (with V LINE) signal to the I SIG output from the harmonic control section 6 dependant on the phase difference between the line voltage and line current. This step is performed by feeding in V LINE through resistor 87 (figure The amount of in-phase signal added must increase with the amount of phase shift between the fundamental component of I LOAD and the voltage V LINE. This can be effected by controlling the magnitude of WO 98/57408 PCT/NZ98/00084 the V LINE signal fed to resistor 87 so that a required amount of in-phase signal is added to I SIG (refer figure 2 figure 4).

Referring to Figure 5, these steps are shown in flow chart form in which it can be seen from step 90 that the phase difference between the voltage from the mains supply V LINE, and the fundamental component of I LOAD is compared, then at step 92 as the absolute difference between these two parameters increases, a greater amount of the voltage component is added to I SIG from the harmonic control section 6 through resistor 87, the output of which is fed to the multiplier 88. Even when the phase difference between the fundamental component of I LOAD and the voltage is zero, some of the voltage phase component is still added to I SIG. At worst this method will only add-slightly too much of the V LINE component to I REF resulting in the AHC performing a slight amount of fundamental phase shifting.

The other functions of the bus regulator section 8 which includes protection section 18, are as follows: 1. Sample the RMS current that the power stage 14 (by means of shunt 5) is drawing or supplying from or to the mains. When this RMS current exceeds a predetermined current limit, eg. 70 amps RMS, the value of the impedance of control resistor 64 is increased so that the maximum value of the power stage current is limited so that it does not exceed the predetermined maximum value.

2. Sample the peak power stage current (by means of shunt 5) being injected or drawn to or from the mains so that if a predetermined maximum, eg. 110 amps, is exceeded, all of the active switching devices (described further below) are switched off. Then, when the peak current falls to a predetermined level below the maximum, switching control is allowed to be activated again. This is shown in Figure 6 where the current locus 94 is shown to rise with respect to time until it reaches a maximum point 96 where the switching devices are all switched off until the current lowers to a predetermined lower level represented by the base of trough 98 before the devices are activated again. As can be seen from Figure 6, this situation may be repeated a number of times depending upon the current that is required to be injected or drawn by the power stage. The WO 98/57408 PCT/NZ98/00084 objective of this part of the control circuitry is to ensure the power stage cannot pass currents that are too high.

Switching control section The switching control section 10 is generally illustrated with reference to figures 9 to 14. Referring to figure 7, I REF from the bus regulator section 8 is provided to this section at step 101 after which a DC offset may be added. At steps 103 and 104 the I REF signal has a selected positive and negative offset respectively added to it so as to create predetermined boundaries or limits as will be described further below. The offsets may be 1 volt in magnitude for example, but this magnitude can be selected by a user to provide variable switching rates at the inverter stage as will be described further below. The steps 103 and 104 thus lead to a signal output corresponding to an upper limit and a lower limit for the requiredmains harmonic compensated current profile.

The upper limit signal from step 103 is fed into the non-inverting input of a comparator 105. The inverting input of comparator 105 is supplied with the I LINE signal referred to with respect to the harmonic control section 6 (refer figure The inverting input of comparator 105 is also supplied with the high frequency switching waveform derived from the shunt 5. Capacitor 91 AC couples the high frequency switching waveform to the inverting input of comparator 105 to ensure that only the high frequency components are passed. This reinforces the high frequency switching signal at this point to provide a high definition signal to the comparator. It also allows filtering of the I LINE signal at earlier stages of the AHC if necessary.

Similarly, the lower limit output from step 104 is provided to the inverting input of comparator 106. The non-inverting input of this comparator is supplied with the I LINE signal and is AC coupled via capacitor 93 to the shunt 5 as described with reference to the inverting input of comparator 105 above. Therefore when the I LINE signal exceeds the upper limit, the output of comparator 105 will go low. Similarly, when the I LINE signal is lower than the lower limit, the output of comparator 106 will go low. The outputs of comparators 105 and 106 are fed to logic circuitry comprising four NOR gates two gates 107, gate 107A and gate 107B and by an OR gate 108. This logic WO 98/57408 PCT/NZ98/00084 circuitry also has inputs from zero crossing detector circuitry generally referenced 109 which indicates when the mains voltage V LINE is in the positive half cycle, and when it is the negative half cycle.

Logic circuitry senses the line voltage via resistors 120. Two zener diodes, having a reverse breakdown voltage of 15 volts, for example, provide a +15V -15V square wave at node 122, the waveform being +15V when V LINE is in the positive half cycle and -15V when V LINE is in the negative half cycle. This square wave output is fed into comparator 124 which has positive feedback resistor 126 to improve the characteristics of this waveform and reduce any tendency of the comparator to oscillate. Output 128 of comparator 124 is fed to an inverter 130 and to an XOR gate 132. The output of inverter 130 is fed to another XOR gate 134. The other two inputs of each of the gates are linked together, being fed with the output of circuitry 136 which will be described further below. Assuming that the output of circuitry 136 is in the low state, then the square wave representative of V LINE polarity, and the inverted waveform from inverter 130, will create the following outputs at gates 107A, 107B and 108: NOR gate 107A; output goes high when I LINE exceeds I UPPER and the mains voltage V LINE is in the positive half cycle; otherwise low.

OR gate 108; output goes high when I LINE exceeds I upper in the negative half V LINE cycle or when I LINE is less that I LOWER in the positive half V LINE cycle; otherwise low.

NOR gate 107B; output goes high when I LINE is less than I LOWER and mains voltage is V LINE in negative half cycle; otherwise low.

Referring now to logic circuitry 136 of figure 7, the output of gate 108 is supplied to resistor 138 and capacitor 140 which have a selected time constant. If the output of OR gate 108 is high for a selected period, for example 25 microseconds, then the output of amplifier 142 then goes from it's normally low state to the high state. If the output of OR gate 108 changes to the low state again within the predetermined time period then the charge on capacitor 140 is simply dissipated through diode 144 without the output of amplifier 142 going high.

WO 98/57408 PCT/NZ98/00084 The result of the output of amplifier 142 going high is that gate 108 will go low and gate 107A will go high in the negative half voltage cycle; or gate 108 will go low and gate 107B will go high in the positive half voltage cycle.

Turning to figure 8, the outputs of gates 107A, 108 and 107B are fed into the set inputs of flipflops RA, RB and RC which in turn are provided to AND gates 109, 110 and 111.

The outputs of these AND gates control three switches, a first switch A, a second switch C and a third switch B, shown-in figure 9. Accordingly, switch A in figure 9 is turned on when the output of gate 109 is high, switch B is turned on when the output of gate 110 is high, and switch C is turned on when the output of gate 111 is high, otherwise they are off.

Thus, referring to figure 9, switches A and B typically operate over a positive half cycle of the mains voltage cycle. Without considering the influence of circuitry 136 of figure 7, if switch A alone is turned on, then the current being supplied to the load by the mains M will reduce to reduce I LINE as load power is being supplied by the AHC.

Similarly if switch B is on I LINE will increase, and if switch B is off and switch C is on when the voltage is in the negative half cycle, I LINE will reduce.

Referring again to figure 7, it will be seen that in the positive half voltage cycle, comparator 105 is routed through to switch A and comparator 106 acts on switch B. In the negative half cycle, comparator 105 acts on switch B and comparator 106 acts on switch C. Comparators 105 and 106 have active low outputs which are inverted by the NOR gates. Because comparators 105 and 106 only go low when the I UPPER or I LOWER band is crossed and are high when I LINE is within this band, a D type flipflop is used to latch the last switching command. Therefore when a SET set flipflop output high) is put on a flipflop RA, its Q output goes high and the Q outputs of RB and RC are reset to a low state via the diodes D.

The stop line forces the outputs of the AND gates low and the IR circuit issues a reset command in the three flipflops RA, RB and RC to ensure a stop (in which case all of the switches in the power stage are switched to the off state).

WO 98/57408 PCT/NZ98/00084 As can be seen from figure 9 the three switch power stage allows three output voltages to be applied across the mains via the output inductor L; DC voltage (which in the embodiment described is preferably +410 volts); 0 volts (neutral); and DC voltage (which in the embodiment described is preferably -410 volts). The inductance of the output inductor L is selected to provide a desired rate of change of current. Thus referring to figure 11 which is a simplified model of the power stage shown in figure 9, we see the situation where switch A is active while switch B is open, so that current I is returned to the mains supply through inductor L. The voltage of the capacitor buses is chosen to be greater than the voltage of the mains supply M.

It will be seen that controlling the positive and negative offsets at steps 103 and 104 (referring to figure 7) allows the switching band for the power stage to be widened or narrowed. This allows the maximum switching frequency of the power stage 14 to be controlled. The switching frequency is determined by the DC bus voltage, the size of the output inductor L, and the width of the switching band which determines the value of the ripple current desired. With reference to figure 11, when current I is flowing as shown, the rate of change of current flow is determined by the equation V/L di/dt.

This is shown by the upwardly sloping line in figure 12 in which the current I can be seen ramping upwardly from the lower switching limit to the upper switching limit while switch A is on.

When switch A is turned off and switch B is turned on, which is indicated by the downwardly sloping line in figure 12, the current I ramps down at-the rate V/L di/dt and in this case the voltage V will be the mains voltage rather than the difference between the voltage of the capacitor bank and the mains supply.

Referring again to circuitry 136 of figure 7, this circuitry effectively allows a faster change in I LINE if switch B has been on for a long time period. Occaisionally, the difference in voltage between V LINE and neutral may be insufficient to ensure a satisfactory change in the rate of change of I LINE. To increase performance, circuitry 136 monitors the length of time for which switch B remains on. If the predetermined limit imposed by resistor 138 and capacitor 140 is exceeded, then the circuitry forces switch B off and activates switch A if V LINE is in the negative half cycle, or activates switch C if V LINE is in the positive half cycle. Thus the voltage buses augment the supply voltage to assist in forcing a more rapid change in I LINE.

WO 98/57408 PCT/NZ98/00084 It can be seen that the wider the switching band, the more time that is required for the current to traverse between the lower and upper limits. Therefore, a wider band corresponds to a lower switching frequency. Accordingly, frequency control is provided by having a frequency to voltage converter (not shown) sample the frequency of one of the flipflops shown in figure 8, for example flipflop RB, by sampling the Q output of this flipflop. If the frequency of the change in flipflop output exceeds a predetermined maximum, then the offsets at steps 103 and 104 in figure 7 can be widened by the circuity so as to reduce the frequency. Conversely, the frequency can also be maintained above a predetermined minimum level if desired.

Power Stage Referring to figure 13, the power stage 14 (figure 1) of the apparatus is shown in diagrammatic form. The power stage may generally be referred to as a three level inverter. The operation has been described generally with reference to figure 9, but the operation will now be described in more detail below.

The power stage also includes a small known resistor capacitor (RC) snubbers across switch A, switch B and switch C, to lessen fast rising voltages at turn off and to generally reduce RFI emissions. Furthermore, switches A and C may comprise more than one IGBT, for example two IGBTs may be connected in parallel with a single separate anti-parallel diode. Also, switch B may comprise more than one FET, for example two or more FETs in parallel inside the diode bridge.

Furthermore, figure 9 only shows one switching cell. In some applications it is preferable use two or more switching cells per phase and combine the outputs of these cells to increase capability, for example 100 amps peak or 70 amps RMS switching at up to 20 kilohertz. In figure 10 a schematic for combining cells is shown using a combining choke 146. In use currents 148 from the cells flow through the combining choke to the output choke as shown in figure 10. The combining choke has a high inductance and ensures that both cells carry the same current during switching transitions so that excessive current flow will not occur should one cell switch earlier than the other.

WO 98/57408 PCT/NZ98/00084 The control of the switching devices in the power stage 14 referred to above have significant advantages in that it allows the power stage to be shifted from one desired current to another very quickly (it is possible to do this within one switching cycle) without over shoot or ringing. Thus a very fast response is available. This cannot be done in most PWM inverter systems.

The actual line current waveform thus produced by the AHC will be as shown in exaggerated form by the I LINE waveforms at the output of offset adders 103 and 104 (figure 7).

It will be seen that the present invention provides considerable advantages over the prior art, in particular the three level inverter structure provides is very efficient, using a minimal number of switching devices while applying three output voltages. The control strategy allows rapid response to transients while still being relatively straightforward to implement. Thus the control implementation varies the inverter output current far more rapidly and stably than can be achieved with conventional fixed frequency PWM closed loop control.

Claims (13)

1. Harmonic compensation apparatus to remove at least one harmonic component from an alternating current power distribution system, the power distribution system having a line current waveform including a fundamental and at least one harmonic frequency component flowing through a line connected to a load, the apparatus including; control signal generating means for producing a control signal corresponding to a line current or line voltage waveform substantially devoid of the at least one harmonic component and establishing predetermined boundaries relative to the control signal, the predetermined boundaries corresponding to desired boundaries for a line current or a line voltage substantially devoid of the at least one harmonic component, switching means for supplying or drawing current to or from the line, and switching control means to control the switching means to supply or draw current to or from the line to create a line current or line voltage which is within the desired boundaries and which is substantially devoid of the at least one harmonic component.

2. Harmonic compensation apparatus as claimed in claim 1 wherein the line current and the current being drawn from or supplied to the line by the apparatus is sensed and the load current is derived therefrom by algebraic subtraction means.

3. Harmonic compensation apparatus as claimed in claim 1 wherein the load current and the current being drawn from or supplied to the line by the apparatus is sensed and the line current is derived therefrom by algebraic adding means.

4. Harmonic compensation apparatus as claimed in any one of the preceding claims wherein the control signal comprises a substantial sinusoid generated by the control signal generating means having a frequency and/or phase substantially corresponding to the fundamental frequency component of the line current. Harmonic compensation apparatus as claimed in any one of the preceding claims wherein the control signal generating means establishes the predetermined boundaries by adding and subtracting predetermined offsets to the control signal.

WO 98/57408 PCT/NZ98/00084

6. Harmonic compensation apparatus to remove at least one harmonic component from an alternating current power distribution system, the power distribution system having a current waveform including a fundamental and at least one harmonic frequency component flowing through a line connected to a load, the apparatus including; a first controllable switching means for increasing or reducing current in the line in a positive half voltage cycle of the system, a second controllable switching means for increasing or reducing the line current in a negative half voltage cycle, a third controllable switching means for increasing or reducing line current in both the positive and negative half voltage cycles, and control means for controlling the switching means to compensate for the at least one harmonic component.

7. Harmonic compensation apparatus as claimed in claim 6 wherein the control means comprises control signal generating means for producing a control signal corresponding to a line current or line voltage waveform substantially devoid of the at least one harmonic component and establishing predetermined boundaries relative to the control signal, the predetermined boundaries corresponding to desired boundaries for a line current or a line voltage substantially devoid of the at least one harmonic component, and switching control means to control the switching means to create a line current or line voltage which is within the desired boundaries and which is substantially devoid of the at least one harmonic component.

8. A method of compensating for at least one harmonic component from an alternating current power distribution system, the power distribution system having a current waveform including a fundamental and at least one harmonic frequency component flowing through a line connected to a load, the method comprising the steps of; producing a control signal corresponding to a desired line current or line voltage waveform which is substantially devoid of the at least one harmonic component, establishing predetermined boundaries relative to the control signal, the predetermined boundaries corresponding to desired boundaries for a line current or a line voltage substantially devoid of the at least one harmonic component, and WO 98/57408 PCT/NZ98/00084 supplying or drawing current to or from the line to create-a line current or line voltage which is within the desired boundaries and which is substantially devoid of the at least one harmonic component.

9. A method as claimed in claim 8 wherein the line current and the current being drawn from or supplied to the line by the apparatus is sensed and the load current is derived therefrom by algebraic subtraction means.

A method as claimed in claim 8 wherein the load current and the current being drawn from or supplied to the line by the apparatus is sensed and the line current is derived therefrom by algebraic adding means.

11. A method as claimed in any one of claims 8 to 10 including the step-of generating a substantial sinusoid having a frequency and/or phase substantially corresponding to the fundamental component of the load current.

12. A method as claimed in any one of claims 8 to 11 including the step of establishing predetermined boundaries by adding and subtracting a predetermined offsets to the control signal.

13.. Any novel feature or element or combination of features or elements described herein.