AU7246396A - Self-modifying code handling system - Google Patents

Self-modifying code handling system

Info

Publication number
AU7246396A
AU7246396A AU72463/96A AU7246396A AU7246396A AU 7246396 A AU7246396 A AU 7246396A AU 72463/96 A AU72463/96 A AU 72463/96A AU 7246396 A AU7246396 A AU 7246396A AU 7246396 A AU7246396 A AU 7246396A
Authority
AU
Australia
Prior art keywords
self
handling system
modifying code
code handling
modifying
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
AU72463/96A
Other languages
English (en)
Inventor
Amos Ben-Meir
John G. Favor
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Advanced Micro Devices Inc
Original Assignee
Advanced Micro Devices Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Micro Devices Inc filed Critical Advanced Micro Devices Inc
Publication of AU7246396A publication Critical patent/AU7246396A/en
Abandoned legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3818—Decoding for concurrent execution
    • G06F9/382—Pipelined decoding, e.g. using predecoding
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30145—Instruction analysis, e.g. decoding, instruction word fields
    • G06F9/30149—Instruction analysis, e.g. decoding, instruction word fields of variable length instructions
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/3017—Runtime instruction translation, e.g. macros
    • G06F9/30174—Runtime instruction translation, e.g. macros for non-native instruction set, e.g. Javabyte, legacy code
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3802—Instruction prefetching
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3802—Instruction prefetching
    • G06F9/3812—Instruction prefetching with instruction modification, e.g. store into instruction stream
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3818—Decoding for concurrent execution
    • G06F9/3822—Parallel decoding, e.g. parallel decode units
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3853—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution of compound instructions

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Advance Control (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Executing Machine-Instructions (AREA)
AU72463/96A 1995-10-06 1996-10-03 Self-modifying code handling system Abandoned AU7246396A (en)

Applications Claiming Priority (7)

Application Number Priority Date Filing Date Title
US005069 1987-01-20
US506995P 1995-10-06 1995-10-06
US502195P 1995-10-10 1995-10-10
US005021 1995-10-10
US08/592,150 US5826073A (en) 1995-10-06 1996-01-26 Self-modifying code handling system
PCT/US1996/015420 WO1997013198A1 (en) 1995-10-06 1996-10-03 Self-modifying code handling system
US592150 2000-06-12

Publications (1)

Publication Number Publication Date
AU7246396A true AU7246396A (en) 1997-04-28

Family

ID=27357779

Family Applications (1)

Application Number Title Priority Date Filing Date
AU72463/96A Abandoned AU7246396A (en) 1995-10-06 1996-10-03 Self-modifying code handling system

Country Status (6)

Country Link
US (1) US5826073A (enExample)
EP (1) EP0853785B1 (enExample)
JP (1) JP3720370B2 (enExample)
AU (1) AU7246396A (enExample)
DE (1) DE69612991T2 (enExample)
WO (1) WO1997013198A1 (enExample)

Families Citing this family (30)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5758349A (en) * 1995-12-27 1998-05-26 International Business Machines Corporation Process and system for run-time inheritance and disinheritance of methods and data
US6009516A (en) * 1996-10-21 1999-12-28 Texas Instruments Incorporated Pipelined microprocessor with efficient self-modifying code detection and handling
US6170055B1 (en) 1997-11-03 2001-01-02 Iomega Corporation System for computer recovery using removable high capacity media
US7941647B2 (en) 1999-01-28 2011-05-10 Ati Technologies Ulc Computer for executing two instruction sets and adds a macroinstruction end marker for performing iterations after loop termination
US8074055B1 (en) 1999-01-28 2011-12-06 Ati Technologies Ulc Altering data storage conventions of a processor when execution flows from first architecture code to second architecture code
US8065504B2 (en) 1999-01-28 2011-11-22 Ati International Srl Using on-chip and off-chip look-up tables indexed by instruction address to control instruction execution in a processor
US8127121B2 (en) 1999-01-28 2012-02-28 Ati Technologies Ulc Apparatus for executing programs for a first computer architechture on a computer of a second architechture
US6671665B1 (en) * 1999-02-19 2003-12-30 Texas Instruments Incorporated Emulation system with search and identification of optional emulation peripherals
US6850647B1 (en) * 1999-07-30 2005-02-01 Michael L. Gough System, method and article of manufacture for decompressing digital camera sensor data
JP3739607B2 (ja) * 1999-08-24 2006-01-25 富士通株式会社 情報処理装置
US6629175B1 (en) * 2000-04-14 2003-09-30 International Business Machines Corporation Efficient adapter context switching
US7360028B1 (en) * 2000-05-05 2008-04-15 Sun Microsystems, Inc. Explicit store-to-instruction-space instruction for self-modifying code and ensuring memory coherence between instruction cache and shared memory using a no-snoop protocol
US6807623B2 (en) * 2000-07-27 2004-10-19 Matsushita Electric Industrial Co., Ltd. Data processing control system, controller, data processing control method, program, and medium
US20030093775A1 (en) * 2001-11-14 2003-05-15 Ronald Hilton Processing of self-modifying code under emulation
US6543034B1 (en) * 2001-11-30 2003-04-01 Koninklijke Philips Electronics N.V. Multi-environment testing with a responder
US7251594B2 (en) * 2001-12-21 2007-07-31 Hitachi, Ltd. Execution time modification of instruction emulation parameters
US7260217B1 (en) * 2002-03-01 2007-08-21 Cavium Networks, Inc. Speculative execution for data ciphering operations
CA2418255A1 (en) * 2003-01-31 2004-07-31 Ibm Canada Limited - Ibm Canada Limitee Tracking and maintaining related and derivative code
US20040163082A1 (en) * 2003-02-13 2004-08-19 Marc Tremblay Commit instruction to support transactional program execution
US7711990B1 (en) * 2005-12-13 2010-05-04 Nvidia Corporation Apparatus and method for debugging a graphics processing unit in response to a debug instruction
US8516229B2 (en) * 2010-02-05 2013-08-20 International Business Machines Corporation Two pass test case generation using self-modifying instruction replacement
US9436476B2 (en) 2013-03-15 2016-09-06 Soft Machines Inc. Method and apparatus for sorting elements in hardware structures
US20140281116A1 (en) 2013-03-15 2014-09-18 Soft Machines, Inc. Method and Apparatus to Speed up the Load Access and Data Return Speed Path Using Early Lower Address Bits
US9747212B2 (en) * 2013-03-15 2017-08-29 International Business Machines Corporation Virtual unifed instruction and data caches including storing program instructions and memory address in CAM indicated by store instruction containing bit directly indicating self modifying code
US9582322B2 (en) 2013-03-15 2017-02-28 Soft Machines Inc. Method and apparatus to avoid deadlock during instruction scheduling using dynamic port remapping
US9627038B2 (en) 2013-03-15 2017-04-18 Intel Corporation Multiport memory cell having improved density area
US9946538B2 (en) * 2014-05-12 2018-04-17 Intel Corporation Method and apparatus for providing hardware support for self-modifying code
CN104951276B (zh) * 2015-06-24 2017-05-31 福州瑞芯微电子股份有限公司 一种芯片指令高速缓存失效的检测方法及系统
US9996329B2 (en) 2016-02-16 2018-06-12 Microsoft Technology Licensing, Llc Translating atomic read-modify-write accesses
US9986200B1 (en) * 2017-05-11 2018-05-29 Novatek Microelectronics Corp. Method and video conversion system of updating video setting

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0159712B1 (en) * 1984-04-27 1991-01-30 Bull HN Information Systems Inc. Control means in a digital computer
US5226130A (en) * 1990-02-26 1993-07-06 Nexgen Microsystems Method and apparatus for store-into-instruction-stream detection and maintaining branch prediction cache consistency
US5692167A (en) * 1992-07-31 1997-11-25 Intel Corporation Method for verifying the correct processing of pipelined instructions including branch instructions and self-modifying code in a microprocessor
US5434987A (en) * 1993-09-21 1995-07-18 Intel Corporation Method and apparatus for preventing incorrect fetching of an instruction of a self-modifying code sequence with dependency on a bufered store

Also Published As

Publication number Publication date
EP0853785A1 (en) 1998-07-22
JP3720370B2 (ja) 2005-11-24
DE69612991D1 (de) 2001-06-28
EP0853785B1 (en) 2001-05-23
WO1997013198A1 (en) 1997-04-10
JP2001517333A (ja) 2001-10-02
US5826073A (en) 1998-10-20
DE69612991T2 (de) 2002-01-17

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