AU701467B2 - Two-way set-associative cache memory - Google Patents

Two-way set-associative cache memory Download PDF

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Publication number
AU701467B2
AU701467B2 AU17991/95A AU1799195A AU701467B2 AU 701467 B2 AU701467 B2 AU 701467B2 AU 17991/95 A AU17991/95 A AU 17991/95A AU 1799195 A AU1799195 A AU 1799195A AU 701467 B2 AU701467 B2 AU 701467B2
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Australia
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cache
state
array
line
data
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Expired
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AU17991/95A
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AU1799195A (en
Inventor
Konrad K Lai
Wen-Hann Wang
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Intel Corp
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Intel Corp
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Publication of AU701467B2 publication Critical patent/AU701467B2/en
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0864—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches using pseudo-associative means, e.g. set-associative or hashing

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
AU17991/95A 1994-08-11 1995-05-11 Two-way set-associative cache memory Expired AU701467B2 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US288923 1994-08-11
US08/288,923 US5548742A (en) 1994-08-11 1994-08-11 Method and apparatus for combining a direct-mapped cache and a multiple-way cache in a cache memory

Publications (2)

Publication Number Publication Date
AU1799195A AU1799195A (en) 1996-02-22
AU701467B2 true AU701467B2 (en) 1999-01-28

Family

ID=23109244

Family Applications (2)

Application Number Title Priority Date Filing Date
AU17991/95A Expired AU701467B2 (en) 1994-08-11 1995-05-11 Two-way set-associative cache memory
AU32127/95A Abandoned AU3212795A (en) 1994-08-11 1995-08-04 A two-way set-associative cache memory

Family Applications After (1)

Application Number Title Priority Date Filing Date
AU32127/95A Abandoned AU3212795A (en) 1994-08-11 1995-08-04 A two-way set-associative cache memory

Country Status (10)

Country Link
US (1) US5548742A (cg-RX-API-DMAC7.html)
EP (1) EP0775345B1 (cg-RX-API-DMAC7.html)
JP (1) JPH10504124A (cg-RX-API-DMAC7.html)
KR (1) KR100382821B1 (cg-RX-API-DMAC7.html)
AU (2) AU701467B2 (cg-RX-API-DMAC7.html)
DE (1) DE69530776T2 (cg-RX-API-DMAC7.html)
ES (1) ES2201114T3 (cg-RX-API-DMAC7.html)
GB (1) GB2292237A (cg-RX-API-DMAC7.html)
TW (1) TW275689B (cg-RX-API-DMAC7.html)
WO (1) WO1996006390A2 (cg-RX-API-DMAC7.html)

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Also Published As

Publication number Publication date
AU3212795A (en) 1996-03-14
TW275689B (cg-RX-API-DMAC7.html) 1996-05-11
DE69530776T2 (de) 2004-03-25
EP0775345B1 (en) 2003-05-14
KR960008546A (ko) 1996-03-22
GB9510677D0 (en) 1995-07-19
ES2201114T3 (es) 2004-03-16
WO1996006390A2 (en) 1996-02-29
GB2292237A (en) 1996-02-14
EP0775345A2 (en) 1997-05-28
KR100382821B1 (ko) 2003-07-18
EP0775345A4 (en) 1997-07-16
WO1996006390A3 (en) 1996-05-09
DE69530776D1 (de) 2003-06-18
AU1799195A (en) 1996-02-22
JPH10504124A (ja) 1998-04-14
US5548742A (en) 1996-08-20

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