AU625196B2 - A method and circuit board for mounting a semiconductor component - Google Patents

A method and circuit board for mounting a semiconductor component Download PDF

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Publication number
AU625196B2
AU625196B2 AU46118/89A AU4611889A AU625196B2 AU 625196 B2 AU625196 B2 AU 625196B2 AU 46118/89 A AU46118/89 A AU 46118/89A AU 4611889 A AU4611889 A AU 4611889A AU 625196 B2 AU625196 B2 AU 625196B2
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Prior art keywords
circuit board
package
holes
board
heat
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AU46118/89A
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AU4611889A (en
Inventor
Rolf Heidemann
Erwin Schlag
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Alcatel Lucent NV
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Alcatel NV
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/64—Impedance arrangements
    • H01L23/66—High-frequency adaptations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367—Cooling facilitated by shape of device
    • H01L23/3677—Wire-like or pin-like cooling fins or heat sinks
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0201—Thermal arrangements, e.g. for cooling, heating or preventing overheating
    • H05K1/0203—Cooling of mounted components
    • H05K1/0204—Cooling of mounted components using means for thermal conduction connection in the thickness direction of the substrate
    • H05K1/0206—Cooling of mounted components using means for thermal conduction connection in the thickness direction of the substrate by printed thermal vias
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0201—Thermal arrangements, e.g. for cooling, heating or preventing overheating
    • H05K1/0203—Cooling of mounted components
    • H05K1/0207—Cooling of mounted components using internal conductor planes parallel to the surface for thermal conduction, e.g. power planes
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0213—Electrical arrangements not otherwise provided for
    • H05K1/0237—High frequency adaptations
    • H05K1/0243—Printed circuits associated with mounted high frequency components
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341—Surface mounted components
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
    • H01L2224/48472—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
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    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01014—Silicon [Si]
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    • H01L2924/01—Chemical elements
    • H01L2924/01039—Yttrium [Y]
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    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
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    • H01—ELECTRIC ELEMENTS
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/10251—Elemental semiconductors, i.e. Group IV
    • H01L2924/10253—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1517—Multilayer substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/1615—Shape
    • H01L2924/16195—Flat cap [not enclosing an internal cavity]
    • H—ELECTRICITY
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19041—Component type being a capacitor
    • H—ELECTRICITY
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    • H01L2924/30—Technical effects
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    • H01L2924/30107—Inductance
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    • H01L2924/301—Electrical effects
    • H01L2924/3011—Impedance
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0213—Electrical arrangements not otherwise provided for
    • H05K1/0216—Reduction of cross-talk, noise or electromagnetic interference
    • H05K1/023—Reduction of cross-talk, noise or electromagnetic interference using auxiliary mounted passive components or auxiliary substances
    • H05K1/0231—Capacitors or dielectric substances
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/095—Conductive through-holes or vias
    • H05K2201/09572—Solder filled plated through-hole in the final product
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10621—Components characterised by their electrical contacts
    • H05K2201/10689—Leaded Integrated Circuit [IC] package, e.g. dual-in-line [DIL]
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10954—Other details of electrical connections
    • H05K2201/10969—Metallic case or integral heatsink of component electrically connected to a pad on PCB
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/04—Soldering or other types of metallurgic bonding
    • H05K2203/0455—PTH for surface mount device [SMD], e.g. wherein solder flows through the PTH during mounting
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/42—Plated through-holes or plated via connections
    • H05K3/429—Plated through-holes specially for multilayer circuits, e.g. having connections to inner circuit layers
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Materials Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Manufacturing & Machinery (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
  • Combinations Of Printed Boards (AREA)
  • Structure Of Printed Boards (AREA)
  • Shielding Devices Or Components To Electric Or Magnetic Fields (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)

Abstract

Printed circuit boards in which the components are secured by a sprung mounting plate are known. The mounting plate serves not only as current path but as cooling plate. Such a component fixture is not suitable for high-frequency applications. The problem of the invention is to mount high-speed chips (for frequencies of over 1 GHz), which cannot be built into small microwave housings owing to the requirements to be met for such high frequencies, on a board in such a way a connection suitable for microwave applications and the necessary heat dissipation from the component can be achieved with simple means. The basic idea of the solution is to connect the metallic base surface of the chip housing (2) to the metallic layers of the multilayer printed circuit board (1) via plated-through holes. For this purpose, the printed circuit board (1) is provided with through holes (21) which open into a mounting pad (20) on the printed circuit board (1) and which are in contact with planar conductor tracks (13, 14) in the printed circuit board. The housing base (4) is placed on the mounting pad (20) and the holes (21) are filled with a molten solder. This connects the housing (2) in a thermally and electrically conducting manner to the planar conductor tracks (13, 14). <IMAGE>

Description

COMMONWEALTH OF AUSTRALIA PATENTS ACT 1952-1969 04 0 COMPLETE SPECEV~ICATION FODR THE INVENTION ENTITLED WAP, i r "A METHOD AND CIRCUIT BOARD FOR MOUNTING A SEMICONDUCTOR COMPONENT" The following statement is a full description of this invention, including the best method of performing it known to us:- 1 p r This invention relates to a method for mounting a packaged semiconductor component on a circuit board, and a circuit board with at least one semiconductor component.
With a previously known circuit board, the semiconductor component is fixed by means of a spring clamp to a mounting plate which acts as a heat sink and mounting surface. High-speed circuits using signals in the Gbit/s or GHz range have to satisfy severe requirements. Their semiconductor components also called "chips" below use small microwave packages. These need to have small dimensions (only a few millimetres) to keep the lead inductances small.
1Q Such microwave packages also have a metal base which can dissipate several watts even though the dimensions are small.
Especially with digital circuits, because of the large number of signals involved, a lD "ge number of leads or pins is required. The large number of pins and the small dimensions yield small pin spacings. This raises the prob- Slem of producing transmission paths with the correct characteristic impedance 0o o and good decoupling in spite of the small pin spacings.
0400 o The invention arises out of the need to provide a method, and a circuit 0 0 board, for the mounting of high-speed chips, particularly those in microwave 4 packages.
According to the invention, there is provided a method of mounting a packaged semiconductor on a circuit board, ensuring that the package is in contact with a heat conducting component, comprising the steps of: providing the circuit board with through-holes on a mounting surface arranged on the board, the holes touching flat conductors within the board; placing the base of the package on the mounting surface; filling the holes with liquid solder, thus connecting the package thermally and electrically with the flat conductors.
2, According to a further aspect of the invention there is provided a circuit board with at least one semiconductor component housed in a package connected with a heat sink, wherein the package rests on the mounting surface of the circuit board, said circuit board having several through-holes on the mounting surface, the holes touching flat conductors within the board, said holes being filled with liquid solder, which provides a thermal and electrical connection between the package and at least some of the flat conductors.
The particular advantages of the invention are that it provides an efficient heat transfer on the one hand, and connections suitable for microwaves on the other hand, both with a single process and without additional steps.
In order that the invention may be readily carried into effect, an embodiment thereof will now be described in relation to the drawings, in which: Figure 1 shows an enlarged partial section of a circuit board according to the invention; Figure 2 shows an enlarged plan view of a part of the circuit board of Figure 1.
A package 2 containing a silicon chip 3 is mounted on a circuit board 1 (Figure This package consists of a flat metal base 4, ceramic walls 5 and a metal lid 6.
Because of the requirements placed on high-speed chip packages, a typical example takes the form of a 32-lead package with a metal base and dimensions of 6 rn x 6 mm x 1 mm.
Moreover, with high-speed circuits special requirements apply not only to the package, but also to the connections and the mounting of the package on the circuit board: the signal connections must be strip lines of the correct characteristic impedance, right up to the package leads; the terminating resistances for the signal lines must be placed very close to the package leads, in order to ensure reflection-free terminations; 3 l: the required separation capacitors must also be mounted close to the package leads; blocking capacitors for the supply voltage must likewise be placed close to the package leads, in order to keep troublesome line inductances small; it is necessary to provide an extended-surface, and therefore low-inductance, connection for ground and supply voltage; the package base must be connected to the negative supply voltage; good heat removal must be achieved from the package base, without a costly mechanical design; the package attachment must be simple and easy to make.
As a result of these requirements, the area near the package is fully taken up with signal lines and surface-mounting components. The cooling prob- Slem is aggravated by the small base area and the negative supply voltage at Sthe package base. Therefore, a conventional solution using a heat sink and Sclamping arrangement is not possible.
The circuit board 1 according to the invention is so designed that it fulfills the requirement for connections suitable for microwaves, as well as ensuring adequate cooling of the chip 3.
For a package 2 with 32 leads and the dimensions given above, the lead spacing is only 0.76 mm. The circuit board 1 is manufactured as a 6-layer multilayer board using the standardised epoxy dielectric material FR4. Three layers of epoxy laminate 8, 9, 10 (each copper-clad on both sides) are joined by two adhesive layers 7. There are thus six metal layers separated by dielectric; the first (top) layer 11 containing the connections in the form of striplines; a second layer 12 connected to ground; third and fourth layers, 13 and 14, connected to a first supply voltage UEE (eg. 5 a fifth layer 15 connected to second supply voltage UT (eg. 2V); and a sixth (bottom) layer 16 connected to ground.
4 i iii-~ -YILmrr-i*rYrrrrr-j--^ The dielectric layers 8 to 10 are 0.36 mm thick, resulting in a stripline width of 0.64 mm for the required characteristic impedance. With these dimensions, all signal connections are kept as 50 Ohm striplines right up to the leads 18 of the semiconductor die or chip 3. Several surface-mounting components 19, required for proper operation of the high-speed circuit, are also arranged close to the package 2. Since only the top metal layer 11 is required for signal connections to the chip 3, the remaining five metal layers are left as complete layers. They are therefore well suited for ground and supply voltage connections on the one hand, and for removal of the heat generated by chip 3 on the other hand.
The circuit board 1 has a mounting surface 20, on which the chip package 2 rests with its metal base 4. Within the mounting surface 20 there are several through-holes 21. These holes 21 are evenly distributed over the area of the mounting surface 20; in the example it is an arrangement of 16 holes Swith uniform spacing. The holes 21 are completely filled, froa the back of the board, with liquid solder, thereby soldering the package base 4 to the S mounting surface 20 of the circuit board i. By this means, the completely filled holes 21 provide through-connections. The solder used is an indium-tin solder with a melting point of 1170C.
The through-connections 22 provide good electrical contact as well as a good thermal connection to the package base 4. They contact the two inner metal layers 13 and 14 and are thus connected to the first negative supply voltage. These inner layers 13 and 14 form extended-surface supply planes and, in conjunction with the direct, flat-plane contact to the chip 3 via the base 4, provide a very low-inductance supply connection. Moreover, the metal layers 12, 13 and 15, 16 are ground and supply voltage planes which form very good HF-blocking capacitors with very low lead inductances. Any resonance effects of the blocking capacitors and the series inductances are suppressed by the lossy dielectric of layers 8, 9 and mod L i. The through-connections provide a very good thermal transition between the package base 4 and the inner metal layers 13 and 14, so that the power dissipation of chip 3 can be rapidly conducted away along these metal layers 13, 14. Because of the close proximity of the layers to each other in the multilayer board, the heat is easily distributed to all six metal layers 11 to 16 and then transmitted to the surroundings via the surface. The direction of heatflow from chip 3 to the inner metal layers and thence to the surfaces of circuit board 1 is shown in the drawing by arrows 23, 24 and The dielectric layers 8, 9 and 10 are each 0.36 mm thick. The adhesive layers 7 are each 0.1 mm thick and join the metal-clad dielectric layers 8 to 9 and 9 to 10. The copper cladding layers 11 to 16 are each 0.35 um thick.
This results in a total thickness for the circuit board 1 of 1.6 mm. The other dimensions of the circuit board are 100 mm by 160 mm.
The plan view (Figure 2) shows how the bonding pads of the chip 3 contained in package 2 are connected via the bonding wires 28 to the inner termi- 2 nating pads 29, which are connected to the package leads 18. The leads 18 in 44i turn are connected to signal lines 30 formed as 50-Ohm striplines. In the vicinity of leads 18, surface-mounting components 19 are attached to the signal lines 30. These components are, for example, blocking capacitors, coupling capacitors, or terminating resistors. Some of the package leads 31 are connected to ground via through-holes 32.
Silicon bipolar integrated circuits 3, mounted on a circuit board 1 as described above, were operated successfully with bit-streams up to 2.6 Gbit/s.
With a dissipation of 2 Watts, a thermal resistance of only 13 deg/W was measured from the silicon chip to the surrounding atmosphere. The thermal resistance can be further reduced if the heat is additionally dissipated from a metal plate fitted to the back of the circuit board.
With the mounting system for fast semiconductor components described above, it is possible to use standard multilayer circuit board techniques successfully in the frequency range up to several GHz/s. It is therefore not 6 necessary to resort to costly ceramic packages and circuit boards, despite the electrical and thermal requirements of the design.
;t

Claims (9)

1. A method of mounting a semiconductor component housed in a package onto a circuit board, the package including a heat-transfer element arranged to conduct heat from the semiconductor component to the outside of the package, the circuit board including a mounting surface from which through holes extend to the opposite side of the board, the board having at least one conductor surface through which the through holes pass, the method comprising mounting the package on the mounting surface with the heat-transfer element adjacent to the mounting surface, filling the through holes with molten solder so that the package is thermally and electrically connected with the or at least one of the conductor surfaces.
2. A circuit board on which is mounted at least one semiconductor component housed in a package, the package including a heat-transfer element arranged to con- duct heat from the semiconductor component to the outside of the package, the cir- J 'cuit board including a mounting surface from which through holes extend to the 15 opposite side of the board, the board having at least one conductor surface through which the through holes pass, the package being mounted on the mounting surface R: with the heat-transfer element adjacent to the mounting surface, the through holes being filled with solder whereby the or at least one of the conductor surfaces is in thermal and electric contact with the heat-transfer element. 20
3. A circuit board as claimed in claim 2, wherein the holes are uniformly spaced 2 0 over the mounting surface.
4. A circuit board as claimed in claim 2 or claim 3, wherein the circuit board is in the form of a multilayer board.
A circuit board as claimed in any one of claims 2 to 4, wherein the solder contacts one of two flat conductors, one of which is connected to a supply voltage while the other is grounded, and which both extend to near the terminals of the semiconductor component to form a blocking capacitor of very low inductance.
6. A circuit board as claimed in any one of claims 2 to 5 including dielectric lay- ers of thickness x and striplines of width y, with the ratio y x chosen so that the striplines have a predetermined characteristic impedance Z.
7. A circuit board as claimed in claim 6, wherein x 0.36 mm and y 0.64 mm, giving a ratio y x of 1.8 and, for a material with a dielectric constant of 4, a characteristic impedance of Z 50 ohms.
8. A circuit board as claimed in any one of claims 2 to 7, including surface- S. mounted components which are arranged directly around the package. iI t 'F 41 I IT U;e 9
9. A circuit board as claimed in any one of claims 2 to 8, wherein the solder is an indium-tin solder. A circuit board substantially as herein described with reference to Figures 1-2 of the accompanying drawings. DATED THIS SEVENTH DAY OF APRIL 1992 ALCATEL N.V. 1
AU46118/89A 1988-12-24 1989-12-13 A method and circuit board for mounting a semiconductor component Ceased AU625196B2 (en)

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DE3843787A DE3843787A1 (en) 1988-12-24 1988-12-24 METHOD AND PCB FOR MOUNTING A SEMICONDUCTOR COMPONENT
DE3843787 1988-12-24

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AU625196B2 true AU625196B2 (en) 1992-07-02

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JP2840493B2 (en) * 1991-12-27 1998-12-24 株式会社日立製作所 Integrated microwave circuit
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JP3520540B2 (en) * 1993-12-07 2004-04-19 株式会社デンソー Multilayer board
US5642261A (en) * 1993-12-20 1997-06-24 Sgs-Thomson Microelectronics, Inc. Ball-grid-array integrated circuit package with solder-connected thermal conductor
US5741729A (en) * 1994-07-11 1998-04-21 Sun Microsystems, Inc. Ball grid array package for an integrated circuit
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FR2758908B1 (en) * 1997-01-24 1999-04-16 Thomson Csf LOW COST MICROWAVE ENCAPSULATION BOX
JPH1174651A (en) 1997-03-13 1999-03-16 Ibiden Co Ltd Printed wiring board and its manufacture
FR2799339A1 (en) * 1999-10-04 2001-04-06 Sagem Housing for a dissipating power component comprises a metallic casing with aeration holes supporting on one face a radiator and a dissipating power component
KR20020074073A (en) * 2001-03-16 2002-09-28 엘지전자 주식회사 Heat dissipation structure of ic
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EP0352183A1 (en) * 1988-07-20 1990-01-24 Matra Marconi Space France Process for mounting electronic micro components on a support, and intermediate product

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DE58909004D1 (en) 1995-03-23
DE3843787A1 (en) 1990-07-05
EP0376100A2 (en) 1990-07-04
ES2070888T3 (en) 1995-06-16
EP0376100B1 (en) 1995-02-15
ATE118651T1 (en) 1995-03-15
AU4611889A (en) 1990-06-28
EP0376100A3 (en) 1991-07-31

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