AU6211701A - High-speed "maximum a posteriori" (map) architecture with optimized memory size and power consumption - Google Patents
High-speed "maximum a posteriori" (map) architecture with optimized memory size and power consumptionInfo
- Publication number
- AU6211701A AU6211701A AU62117/01A AU6211701A AU6211701A AU 6211701 A AU6211701 A AU 6211701A AU 62117/01 A AU62117/01 A AU 62117/01A AU 6211701 A AU6211701 A AU 6211701A AU 6211701 A AU6211701 A AU 6211701A
- Authority
- AU
- Australia
- Prior art keywords
- posteriori
- architecture
- map
- maximum
- speed
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/37—Decoding methods or techniques, not specific to the particular type of coding provided for in groups H03M13/03 - H03M13/35
- H03M13/39—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes
- H03M13/3905—Maximum a posteriori probability [MAP] decoding or approximations thereof based on trellis or lattice decoding, e.g. forward-backward algorithm, log-MAP decoding, max-log-MAP decoding
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/37—Decoding methods or techniques, not specific to the particular type of coding provided for in groups H03M13/03 - H03M13/35
- H03M13/39—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes
- H03M13/41—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes using the Viterbi algorithm or Viterbi processors
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/37—Decoding methods or techniques, not specific to the particular type of coding provided for in groups H03M13/03 - H03M13/35
- H03M13/39—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes
- H03M13/41—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes using the Viterbi algorithm or Viterbi processors
- H03M13/4107—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes using the Viterbi algorithm or Viterbi processors implementing add, compare, select [ACS] operations
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/65—Purpose and implementation aspects
- H03M13/6502—Reduction of hardware complexity or efficient processing
Landscapes
- Physics & Mathematics (AREA)
- Probability & Statistics with Applications (AREA)
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Error Detection And Correction (AREA)
- Dc Digital Transmission (AREA)
- Cable Transmission Systems, Equalization Of Radio And Reduction Of Echo (AREA)
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
GB0006691 | 2000-03-20 | ||
GB0006691A GB2360858B (en) | 2000-03-20 | 2000-03-20 | High-speed maximum a posteriori (MAP) architecture with optimized memory size and power consumption |
PCT/EP2001/003183 WO2001071924A2 (en) | 2000-03-20 | 2001-03-20 | High-speed 'maximum a posteriori' (map) architecture with optimized memory size and power consumption |
Publications (1)
Publication Number | Publication Date |
---|---|
AU6211701A true AU6211701A (en) | 2001-10-03 |
Family
ID=9888004
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
AU62117/01A Abandoned AU6211701A (en) | 2000-03-20 | 2001-03-20 | High-speed "maximum a posteriori" (map) architecture with optimized memory size and power consumption |
Country Status (3)
Country | Link |
---|---|
AU (1) | AU6211701A (en) |
GB (1) | GB2360858B (en) |
WO (1) | WO2001071924A2 (en) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR2836764B1 (en) * | 2002-03-04 | 2004-07-23 | Wavecom Sa | METHOD FOR PROCESSING A SIGNAL IMPLEMENTING AN APPROACH MAP TYPE ALGORITHM AND CORRESPONDING APPLICATIONS |
Family Cites Families (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR2675971B1 (en) * | 1991-04-23 | 1993-08-06 | France Telecom | CORRECTIVE ERROR CODING METHOD WITH AT LEAST TWO SYSTEMIC CONVOLUTIVE CODES IN PARALLEL, ITERATIVE DECODING METHOD, CORRESPONDING DECODING MODULE AND DECODER. |
DE4437984A1 (en) * | 1994-10-25 | 1996-08-14 | Philips Patentverwaltung | Transmission system with soft output decoding |
US6028899A (en) * | 1995-10-24 | 2000-02-22 | U.S. Philips Corporation | Soft-output decoding transmission system with reduced memory requirement |
US5721746A (en) * | 1996-04-19 | 1998-02-24 | General Electric Company | Optimal soft-output decoder for tail-biting trellis codes |
US5734962A (en) * | 1996-07-17 | 1998-03-31 | General Electric Company | Satellite communications system utilizing parallel concatenated coding |
US5933462A (en) * | 1996-11-06 | 1999-08-03 | Qualcomm Incorporated | Soft decision output decoder for decoding convolutionally encoded codewords |
US6192501B1 (en) * | 1998-08-20 | 2001-02-20 | General Electric Company | High data rate maximum a posteriori decoder for segmented trellis code words |
DE69908820T2 (en) * | 1998-12-18 | 2004-04-15 | Telefonaktiebolaget L M Ericsson (Publ) | FAST, MAXIMUM-A-POSTERIORI DECODING METHOD AND SYSTEM |
-
2000
- 2000-03-20 GB GB0006691A patent/GB2360858B/en not_active Expired - Fee Related
-
2001
- 2001-03-20 WO PCT/EP2001/003183 patent/WO2001071924A2/en active Application Filing
- 2001-03-20 AU AU62117/01A patent/AU6211701A/en not_active Abandoned
Also Published As
Publication number | Publication date |
---|---|
GB0006691D0 (en) | 2000-05-10 |
WO2001071924A2 (en) | 2001-09-27 |
GB2360858A (en) | 2001-10-03 |
WO2001071924A3 (en) | 2002-01-31 |
GB2360858B (en) | 2004-08-18 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
MK6 | Application lapsed section 142(2)(f)/reg. 8.3(3) - pct applic. not entering national phase |