AU6126499A - Method for synchronizing clocks in electronic units connected to a multi processor data bus - Google Patents

Method for synchronizing clocks in electronic units connected to a multi processor data bus

Info

Publication number
AU6126499A
AU6126499A AU61264/99A AU6126499A AU6126499A AU 6126499 A AU6126499 A AU 6126499A AU 61264/99 A AU61264/99 A AU 61264/99A AU 6126499 A AU6126499 A AU 6126499A AU 6126499 A AU6126499 A AU 6126499A
Authority
AU
Australia
Prior art keywords
data bus
units connected
electronic units
processor data
multi processor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
AU61264/99A
Inventor
Steinar Kolnes
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Individual
Original Assignee
Individual
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Individual filed Critical Individual
Publication of AU6126499A publication Critical patent/AU6126499A/en
Abandoned legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/12—Synchronisation of different clock signals provided by a plurality of clock generators

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
AU61264/99A 1999-09-17 1999-09-17 Method for synchronizing clocks in electronic units connected to a multi processor data bus Abandoned AU6126499A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/NO1999/000290 WO2001022202A1 (en) 1999-09-17 1999-09-17 Method for synchronizing clocks in electronic units connected to a multi processor data bus

Publications (1)

Publication Number Publication Date
AU6126499A true AU6126499A (en) 2001-04-24

Family

ID=19907907

Family Applications (1)

Application Number Title Priority Date Filing Date
AU61264/99A Abandoned AU6126499A (en) 1999-09-17 1999-09-17 Method for synchronizing clocks in electronic units connected to a multi processor data bus

Country Status (2)

Country Link
AU (1) AU6126499A (en)
WO (1) WO2001022202A1 (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7080274B2 (en) * 2001-08-23 2006-07-18 Xerox Corporation System architecture and method for synchronization of real-time clocks in a document processing system
US7437587B2 (en) 2005-01-21 2008-10-14 Hewlett-Packard Development Company, L.P. Method and system for updating a value of a slow register to a value of a fast register
CN112202525B (en) * 2020-10-29 2022-11-01 电信科学技术第五研究所有限公司 PPS delay automatic measurement and compensation method of multi-board card equipment

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4882739A (en) * 1988-01-26 1989-11-21 Computer Sports Medicine, Inc. Method for adjusting clocks of multiple data processors to a common time base
US5327468A (en) * 1992-06-19 1994-07-05 Westinghouse Electric Corp. Synchronization of time-of-day clocks in a distributed processing network system
JP3071976B2 (en) * 1993-03-29 2000-07-31 株式会社日立製作所 Bus type clock supply system for communication systems
JPH07281785A (en) * 1994-04-05 1995-10-27 Toshiba Corp Processor system

Also Published As

Publication number Publication date
WO2001022202A1 (en) 2001-03-29

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Legal Events

Date Code Title Description
MK6 Application lapsed section 142(2)(f)/reg. 8.3(3) - pct applic. not entering national phase