AU600531B2 - Adjustable echo canceller - Google Patents

Description

i 60053 COMM~ONWEAL~TH OF AUSTRALIA PATENTS ACT 1952-1969 COM4PLETE SPECIFICATION FOR THE INVENTION ENTITLED "ADJUSTABLE ECHO CANCELLER" ii The following statement is a full description of this invention, including the best method of performing it known to us:- LI~ This invention relates to an adjustable echo canceller coupled between a receive path and a transmit path of a transmitter/receiver equipment, said echo canceller including a digital filter producing a replica signal of an echo signal and a subtractor circuit to subtract said replica signal from said echo signal which appears on said transmit path in response to an input signal applied to said receive path, said input, echo and replica signals being sampled digital signals and each replica signal sample being equal to a sum of terms each constituted by the product of a coefficient of said digital filter and of a factor which is function of said input signal.

Such an echo canceller also called digital hybrid is already known, S e.g. from the article "A 3- um CMOS Digital Codec with Programmable Echo Cancellation and Gain Setting" by P. DEFRAEYE et al, published in the IEEE JOURNAL OF SOLID-STATE CIRCUITS, Vol. SC-20, No 3, June 1985, pages 679 to If 687.

In this article, no information is given about how the coefficients of the filter included in the echo canceller are determined. If this echo canceller is an adaptive one, the filter coefficients may be calculated as described in the Belgian patent No. 896 089. However, such calculations necessitate the use of additional relative complex circuits coupled to the transmitter/receiver equipment. In some cases, this additional expense is considered not to be justified. In these last cases, a possible solution to determine the filter coefficients is to calculate them in such a way that the digital filter wherein they are used provides a replica signal which cancels the echo signal in a satisfactory way on condition that, e.g.

when forming part of telecommunication system, the line used in the transmitter/receiver equipment has a length belonging to a predetermined range of line lengths. Obviously, this solution is not satisfactory when the line length does not belong to this predetermined range, which can be the case in practice.

03 An object of the present invention is to provide an echo canceller of the above type but which is adapted to determine the optimum value of said filter coefficients in a relatively simple way.

According to the invention, this object is achieved by including in the said echo canceller processing means for determining said filter coefficients from values obtained by measuring a plurality of samples of said echo signal and by measa.ring for each echo signal sample said factors of said replica signal sample which, when multiplied by said filter coefficients and summed, cancel said echo signal sample.

Because the echo signal samples as well as the factors used to determine the replica signal samples are both measured, they are dependent on S the real environment wherein the echo canceller is used and are therefore relatively very accurate so that the same is true for the filter coeffi- S cients which are determined by using these measured values.

Preferably to measure each of said factors of said replica signal sample corresponding to an echo signal sample, said processing means apply an input signal to said receive path, successively set the filter coefficient corresponding to said factor equal to a non-zero value and the other filter coefficients to zero, and measure the then obtained replica signal sample which constitutes said factor.

In this way, the individual contribution of each of the filter coefficients to the replica signal sample is known and the factors used to determine the replica signal are measured in a relatively simple manner.

In one embodiment of the invention the processing means are able to perform at least the measurements of the echo signal samples from a location which is common for a plurality of the transmitter/receiver equipments.

In this way, the processing means may be used in common for a plurality of echo cancellers so that the filter coefficients of these echo .CQO_1. cancellers may be determined by making use of a minimum amount of equip-

VS.

9 3 s~ ment. Moreover, any possible update of the processing means has to be performed only once and not for each transmitter/receiver equipment.

Preferably said processing means are able to perform the measurements of said replica signal factors in said transmitter/receiver equipment.

In this way, the accuracy of the measurements of these factors is relatively very high because it is not affected by unwanted interfering signals.

The present invention also relates to a method for determining the coefficients of a digital filter produci g a replica signal of an echo signal and forming part of an echo canceller coupled between a receive path and a transistor path of a transmitter/receiver equipment and further including a subtractor circuit to subtract said replica signal from said echo signal which appears on said transmit path in response to an input signal applied to said receive path, said input, echo and replica signals being sampled digital signals and each replica signal sample being equal to a sum of terms each constituted by the product of one of said filter coefficients and a factor which is function of said input signal.

This method compr'ses the steps of measuring a plurality of samples of said echo signal, measuring for each echo signal sample said factors of said replica signal sample, and determining said filter coefficients from the values obtained by said measurements.

'ihe above mentioned and other objects and features of the invention will become more apparent and the invention itself will be best understood by referring to the following description of an embodiment taken in conjunction with ihe accompanying drawings wherein: Fig. 1 shows part of a telecommunication system with a Digital Signal Processor DSP including an echo canceller according to the invention; Fig. 2 represents the DSP of Fig. 1 and the echo canceller DIH, AD2 in more detail; *1 pr Fig. 3 shows the digital filter DIH included in the echo canceller DIH, AD2 of the DSP of Fig. 2 in detail; and Figs. 4(a) to 4(g) represent various signals waveforms used to illustrate the operation of the echo canceller.

The part of a telecommunication system shown in Fig. 1 includes a Digital Switching Network DSN to which are coupled: an Analog Subscriber Module ASM including a Control Element CEA which is common for 16 Analog Line Controllers ALC of which only one is shown in relative detail; and S a Processor Module PM including a Clock and Tone Module CTM and a second Control Element CEB.

:I DSN, ASM and PM are located in a digital telecommunication exchange and each analog line controller ALC is provided in common for 8 telecommunication lines such as the one shown which has conductors LIO and LI1 con- V nected to a telephone subset TSS.

Each such a controller ALC includes the cascade connection of a Dual Processor Terminal Controller DPTC, a TransCoder and Filter circuit TCF, a Digital Signal Processor DSP, a BIMOS subscriber Line Interface Circuit BLIC and a High Voltage switch Circuit HVC. The DPTC is for instance of Sthe type disclosed in the published Australian patent application no.

i i 38758/85, the TCF is of the type disclosed in the published Australian patent applications nos. 32997/84 and 32999/84, the BLIC is of the type disclosed in the published Australian patent application no. 57130/87 and the HVC is of the type disclosed in the Australian patents nos. 37416/85, 56149/86 and 56146/86. Each pair of DPTC and TCF is common for 8 sets of DSP, BLIC and HVC, the HVC of each set being coupled to a telephone line.

Each HVC includes: I 7 ~~riii-jainar~rru~--~a~xluxin~;nsar-rrr- li 4 pairs of bidirectional switches SWOO/SW01 to SW30/Sw31; line terminals LO and L1 respectively connected to the line conductors LIO and LII; test terminals TO and Tl respectively connected to like named terminals of the Test Circuit TC; ringing terminals RGO and RG1 respectively connected to like named terminals of the Ringing Circuit RC; tip and ring terminals TP and RG respectively connected to like named output terminals of the BLIC; and terminals STA, STB, SRA and SRB respectively connected to like named control terminals of the BLIC.

In HVC, the line terminals LO/L1 are connected to TP/RG via the series connections of SWOO/SW11 respectively. The junction points STB and SRA of SWOO and RO and of SWO1 and Rl are connected to TO and Tl of TC via and SW21 respectively, whilst the junction points STA and SRB of RO and and of R1 and SW11 are connected to RGO and RG1 of RC via SW30 and SW31 respectively. As shown for a switched through connection, series switches SWOO, SW01, SW10 and SW11 are closed whereas the other shunt switches are open. All the switches are controlled by the BLIC so that HVC is able to establish either one of the following connections: between TSS and BLIC; between TSS and TC; between TSS and RC; between BLIC and TC; and between BLIC and RC; The test circuit TC includes, amongst other circuits, a dummy network (not shown) used for simulating the subset TSS during the measurements and 6 thus to avoid the cooperation of the subscriber which should have to offhook his subset TSS, as will be described later. The function of the ringing circuit RC is to apply a ringing signal to the line LIO/LI1.

The subset TSS includes a normally open hook switch HS connected between the line conductors LIO and LI1. The switch HS is closed when the subset TSS is off-hook.

The clock and tone module CTM forming part of Processor Module PM includes a Test Signal Analyzer TSA connected to the control element CEB.

TSA includes a memory MM storing data and software programmes such as PROG1 to PROG4 and a processor PR to run these programmes, as will be described later.

The digital signal processor DSP whose block diagram is shown in Fig.

2 has receive and transmit terminals RO and TI connected to like named terminals of the BLIC, and receive and transmit terminals RI and TO connected to like named terminals of the TCF respectively. The DSP is of the type described in detail in the above mentioned article "A 3- um CMOS Digital Codec with Programmable Echo Cancellation and Gain Setting" by P. DEFRAEYE et al.

The DSP mainly includes, between its receive terminals RI and RO the 2G cascade connection of a digital amplifier, interpolator and filter circuit RXF to convert 8 kilobit/second (kb/s) digital signals, received from TCF on terminal RI and which are obtained by sampling, to 32 kb/s digital signals; an interpolator INT to increase the bitrate of these signals to 1 Megabit/second; and a digital-to-analog converter DAC to convert these 1 Megabit/second digital signals to analog signals.

On the other hand, between its transmit terminals TI and TO, DSP mainly includes the cascade connection of an analog subtractor AD1 whose adding input is connected to TI and whose subtracting input is connected to the output of an analog hybrid ANH the input of which is connected to terminal RO; an analog-to-digital converter ADC to convert the analog signals received from the subset TSS to 1 Megabit/second digital signals; a decimator DEC to reduce the frequency of these digital signals to 32 kb/s; a digital subtractor AD2 whose adding input is connected to the output of DEC and whose subtracting input is connected to the output HO of a digital hybrid DIH the input HI of which is connected between RXF and INT; and a digital filter, decimator and amplifier circuit TXF to convert the 32 kb/s digital signals to 8 kb/s digital signals prior to sending them to

TCF.

The analog hybrid ANH is able to perform echo cancellation on analog signals transmitted to TSS via RO and received back as echo signals in DSP at terminal TI, whilst the purpose of the digital hybrid DIH is to cancel the excess of echo signals remaining after their passage through AD1. DIH is mainly constituted by a digital filter the coefficients of which are stored in an Auxiliary Memory AM which forms part of DSP and is coupled to

DIH.

The digital hybrid DIH is shown in detail in Fig. 3. It mainly includes a 4-tap Finite Impulse Response digital filter FIR which is connected in parallel with a first order Infinite Impulse Response digital filter IIR. More particularly, DIH includes between its terminal HI and HO the series connection of a delay and decimator circuit DCH, the filter FIR 8 in parallel with the filter IIR, and an interpolator ITH. The delay and decimator circuit DCH reduces to 16 kb/s the bitrate of the 32 kb/s digital input signals at HI by eliminating every second sample, whilst the interpolator ITH increases the bitrate of these signals again to 32 kb/s prior to sampling them to the subtracting input of AD2 via HO. This means that the filters FIR and IIR operate at 16 kb/s instead of at 32 kb/s. By proceeding in his way their construction may be simplified.

The 4-tap filter FIR includes the cascade connection of four delay n circuits of one sampling period Dl, D2, D3 and D4 whose junction points are S 10 connected to distinct adding inputs of a multi-input adder Al via respective multipliers Ml to M4. The filter coefficients aO, al, a2 and a3 are applied to second inputs of Ml, M2, M3 and M4 respectively. These coefficients each may have a value ranging between -2 and +2 are are stored in the auxiliary memory AM of the DSP.

|I The first order filter IIR includes between DCH and a fifth adding input of Al (FIR) the series connection of an adder A3, a delay circuit of one sampling period D5, and a multiplier M5. A scaling factor or filter coefficient B is applied to a second input of M5 and the output of D5 is fed back to a second adding input of A3 via a multiplier M6. The coefficient B of the filter IIR may have a value ranging between 0 and +1 because only low-pass filter characteristics have to be generated. A coefficient A which is a pole of the filter IIR is applied to a second input of M6. These coefficients A and B are also stored in the auxiliary memory AM of the DSP.

As is well known in the digital filter art, the value of the output signal yF of the filter FIR at a time kT may be written: yF[kT] a0.x[(k-1)T] al.x[(k-2)T] a2.x[(k-3)T] a3.x[(k-4)T] (1) where x[kT] is the value of an input sequence x(t) at a discrete time kT; is the value of x[kT] delayed by a delay equal to nT; with k 0, 1, 2, 3, and n 1, 2, 3, 4, Also the value of the output signal yl of the filter IIR at a time kT may be written k y [kT] B l A (2) I N=1 where is the value of x[kT] delayed by a delay equal to NT.

It should be noted that in a preferred embodiment, the input sequence x(t) is a digitized and sampled version of an analog pulse signal which has a total duration of 4 milliseconds or 32 x 125 microseconds and a pulse duration of 125 microseconds, the sampling being performed once per frame always during a same channel. The duration of a frame of a Time Division Multiplex (TDM) transmission is 125 microseconds, each frame comprising 32 channels. In practice, to increase the accuracy of the measurement, the analog pulse signal is for instance repeated 30 times and thus generates analog output signals of which only the 10 last signals are considered to calculate the average in order to obtain a mean analog output signal. The sampled and digitized version of this mean analog output signal is an output sequence y(t).

Because the filters FIR and IIR are connected in parallel the global output signal may be written: y[kT] ypFkT] yi[kT] (3) y[kT] a0.x[(k-1)T] al.x[(k-2)T] a2.x[(k-3)T] k N-I a3.x[(k-4)T] B- 1A (4) N=1 This means that the FIR/IIR filter network is able to suppress at any discrete time kT the echo signal which then has the value y[kT] produced by the input signal x(t) when the filter coefficients have such a value that the relation is satisfied. Indeed, the signal at the output terminal HO of DIH is then an exact replica of the echo signal appearing at the output of the decimator DEC (Fig. 2) and since these two signals are subtracted from each other in the digital subtractor AD2 no echo signal will appear at the output of the latter AD2 and thus also at the output of the

DSP.

At the initialization of the telecommunication system, a standard set of filter coefficients is loaded in the auxiliary memory AM of the DSP.

These coefficients are verified at regular time intervals by a maintenance procedure during which a loop is established between TSA and the test circuit TC by closing the switches SW10/SW11 and SW20/SW21 and by opening the switches SWOO/SW01 and SW30/SW31. Under the control of the programme PROG1, a pulse sequence, e.g. as the one mentioned above, is then transmitted from TSA to TC and received back in TSA as a sampled echo signal. The transhybrid loss of DIH is checked by comparing the electric power of this echo signal with a predetermined power value stored in a memory (not shown) of the exchange. If the power of the received signal is less than the predetermined value, e.g. for a transhybrid loss of -30 dB, the coefficients S of the filters FIR and IIR are considered to be satisfactory and are therefore not modified. In the other case, the filter coefficients have to be modified. This is then done automatically during the maintenance procedure 'i 20 'hich operates as described below by using the dummy network of the test circuit TC.

Also on complaints of the subscriber or on decision of the system supervisor the filter coefficients may be updated. In these cases, an operator starts manually the procedure to modify the filter coefficients.

Software programmes PROG2 to PROG4 are executed during the modification procedure in order to determine a new set of filter coefficients a0 to a3 and B. It is to be noted that the coefficient A which is a pole of the filter IIR is not modified by these programmes notably for stability reasons.

In principle, the 5 filter coefficients aO to a3 and B may be determined in TSA by measuring the echo signal or output sequence y(t) received back from TSS and to be compensated by the hybrid DIH, and by measuring the contribution of each of these filter coefficients to the value, e.g. y[kT], of the replica of this echo signal which has to be produced by DIH at that moment, i.e. by determining the factors etc. multiplying these filter coefficients in the above equation By performing the latter measurements for 5 distinct values of k, the 5 filter coefficients may be calculated from 5 equations similar to which may then be written.

The measurements in TSA of the contribution of each of the filter coefficients to the replica of the echo signal are not very accurate because of the influence of noise introduced in the circuitry of the telecommunication system. For this reason, it is preferred to perform these measureji .ments in laboratory where the influence of the analog part can be inhibited by performing a separation at the chip level in order to isolate the dig- K' ital hybrid and by measuring between the terminals RI and TO of the DSP.

I It is to be noted that the contribution of the filter coefficients to the signal generated by DIH is invariable for all the chips of a same design so 2C that these measurements in laboratory has to be performed only once. In this case of laboratory measurements, the delay introduced by the circuitry linking TSA to RI and TO is neglected so that one does not exactly know which value y[kT] of y(t) is cancelled by the measured contributions. For this reason, the measurements in laboratory necessitates an additional measurement of the last mentioned delay.

SFor the above mentioned reasons, the following operations are performed under the control of the programmes PROG2 to PROG4 12

A

i under the control of PROG2 the contribution of each of the coefficients aO to a3 and B to the output signal of DIH is measured only once in laboratory between the terminals RI and TO coupled to DIH; under the control of PROG3 the delay produced by the circuitry connecting TSA to RI, TO, and which has been neglected during the execution of i PROG2, is measured in TSA after a loop has been established between TSA j and DSP; and Sunder the control of PROG4 the real echo signal y(t) to be cancelled by DIH is measured in TSA after a loop has been established between TSA and TSS, and new filter coefficients aO to a3 and B are calculated.

The programmes PROG2 to PROG4 are now considered in relative detail.

PROG2 After the digital hybrid DIH, the digital subtractor AD2 and the circuits RXF and TXF have been isolated from the other circuitry of the exchange, an above mentioned input sequence x(t) of which part of a sequence period is represented in Fig. 4(a) is applied to the terminal RI.

The filter coefficient aO is then made equal to 1 whereas the others are maintained on 0 so that the successive sample values then received on terminal TO and shown in Fig. 4(b) only are the contribution of the coefficient aO to the successive sample values y[kT] with k=0, 1, 2, of the output signal y(t) of DIH. The other filter coefficients al to a3 and B are likewise each successively made equal to 1 while the remaining coefficients are then maintained on 0, and their contributions to the output signal y(t) of DIH are represented in the Figs. 4(c) to 4(f) respective'.

As follows from the above relation the contributions of the filter coefficients a0 to a3 and B to the output signal y(t) of DIH and thus also to the cancelling of the value y[kT] of the identical echo signal y(t) at the moment kT are respectively (6) i 1- m i (7) (8) k (9) N=1.

PROG3 Under the control of this programme, the above mentioned delay introduced by the circuitry linking TSA to the terminals RI and TO is measured. In this connection, it should be noted that because of the time di- Svision multiplex (TDM) transmission of the signal in the digital exchange, Sthis delay depends essentially on the communication path established between ISA and DSP. PROG3 therefore calculates the transmission delay of the signals from TSA to DSP for the same communication path as will be used i during the execution of PROG4.

j To provide a maximum transmission of the signals through the digital hybrid DIH, the filter coefficients al to a3 and B are set to 0, whilst aO i is set to its maximum value, i.e. 2. Then, the above mentioned input sequence x(t) partially shown in Fig. 4(a) is applied to DIH from TSA so that the signal or output sequence y(t) (not shown) received back in TSA is similar, except for the amplitude which is proportional to the va.ue of aO, to i -that represented in Fig. 4(b) but delayed with respect to this signal. In STSA, the value of this delay is obtained by correlating both these signals by means not shown but well known in the art.

It is to be noted that this delay is always expressed by an integer number of discrete time intervals T, i.e. that k is an integer. This delay Sis for instance equal to 4T.

S 'PROG4 The communication path established between TSA and DSP for PROG3 is maintained and extended to TSS, and an above mentioned input sequence x(t) to TSS from TSA.

It is to be noted that during the execution of PROG4, the cooperation of the subscriber, which has to off-hook his subset TSS in order to open the switch HS, is preferred to the dummy network of the test circuit TC be- 14 cause the measurement is then performed on the real subscriber line LIO/LI1.

During the execution of PROG4, the coefficients aO to a3 and B of DIH are all set to 0 so that no signal can pass through DIH and that the sample values received back in TSA are the sample values y[kT], with k 0, 1, 2, of the echo signal y(t) to be compensated by DIH. These various sample values and the resulting echo signal are represented in Fig. 4(g).

Tne above delay determined by PROG3, e.g. equal to 4T, means that the signal waveforms shown in the Figs. 4(b) to 4(f) have to be shifted in time S 10 over a time interval equal to 4T in order that the values of the samples of y(t) shown in Fig. 4(g) should correspond to those of the factors multiply- 1 ing a0 to a3 and B in the above relation For instance, the contributions of the filter coefficients to the cancelling of the sample value G7 (for k=7) in Fig. 4(g) are B7 to F7 (for k=3) shown in Figs. 4(b) to 4(f) respectively so that the equation becomes G7 a0.B7 al.C7 a2.D7 a3.E7 B.F7 In a same way one may write four other similar equations for instance linking the values G8 to Gil of y(t) to the corresponding values of the contributions, i.e. G8 a0.B8 al.C8 a2.D8 a3.E 8 B.F8 (11) G9 a0.B9 al.C9 a2.D9 a3.E9 B.F7 (12) a0.BlO al.C10 a2.D10 a3.E10 B.F10 (13) G11 a0.Bll al.Cll a2.Dll a3.Ell B.F11 (14) From these 5 equations (10) to PROG4 may calculate the values of the filter coefficients a0 to a3 and B.

The new filter coefficients calculated by PROG4 are then substituted for the old ones in the auxiliary memory AM of the DSP mentioned above and PROG1 is run again for verification.

If the new coefficients, calculated with TSS connected to the exchange, meet the requirements, a flag is set to prevent PROG1 from verify- 2 ing them again with respect to the dummy network of TC during a consecutive maintenance procedure and to report erroneous values of the echo response.

While the principles of the invention have been described above in connection with specific apparatus, it is to be clearly understood that this description is made only by way of example and not as a limitation on the scope of the invention.

i i

Claims (10)

1. 2. An echo canceller as claimed in claim i, wherein, to measure each of the factors of the replica signal sample corresponding to an echo signal sample, the processing means apply an input signal to the receive path, successively set the filter coefficient corresponding to the factor equal to a non-zero value and the other filter coefficients to zero, and measure the then obtained replica signal sample which constitutes the factor.
2. 3. An echo canceller as claimed in claim i, wherein to measure each of said echo signal samples said processing means apply an input signal to said receive path set all said filter coefficients equal to zero, and meas- ure the then obtained echo signal.
3. 4. An echo canceller as claimed in claim 1, wherein said processor means measure said echo signal samples and said replica signal factors from different locations and correlate these measurements by determining the de- lay to which a signal is subjected when flowing between both said lo- Scations. 17 r 7 An echo canceller as claimed in any one of claims 1 to 4, wherein said processing means are able to perform at least said measurements of said echo signal samples from a location which is commnon for a plurality of said transmitter/receiver equipments.
4. 6. An echo canceller as claimed in claim 5, wherein the processing means at the common location are coupled to said transmitter/receiver equipments via time division multiplex communication paths.
5. 7. An echo canceller as claimed in any one of claims 1 to 6, wherein said processor means are able to perform the measurements of said replica signal factors in said transmitter/receiver equipment.
6. 8. An echo canceller as claimed in claim 5 or claim 7 as appended to claim 5, wherein said echo signals samples are measured on-site from said common location and that said replica signal factors are measured in the laboratory.
7. 9. An echo canceller as claimed in claim 1, wherein said processing means measure a plurality of echo signal samples equal to the number of filter coefficients to be determined and determine said filter coefficients by solving a same number of mathematical relations each linking a distinct echo signal sample to a corresponding replica signal sample. An echo canceller as claimed in claim i, wherein said input signal is a digitized and sampled version of an analog pulse sequence.
8. 11. A method for determining the coefficients of a digital filter producing a replica signal of an echo signal and forming part of an echo canceller coupled between a receive path and a transmit path of a transmitter/receiver equipment, the echo canceller including a subtractor circuit to subtract said replica signal from said echo signal which appears on said transmit path in response to an input signal applied to said re- ceixve path, said input, echo and replica signals being sampled digital signals and each replica signal sample being equal to a sum of terms each ,constituted by the product of one of said filter coefficients and a factor u18 ~18 which is function of said input signal, characterized in that it comprises the steps of measuring a plurality of samples of said echo signal, measur- ing for each echo signal sample said factors of a corresponding replica signal sample, and determining said filter coefficients from the values ob- tained by said measurements.
9. 12. A method as claimed in claim 11, wherein said filter coefficients are determined in an echo canceller as claimed in any one of claims 1 to
10. 13. An echo canceller substantially as herein described with reference to Figs. 1 to 4 of the accompanying drawings. DATED THIS TWENTY-EIGHTH DAY OF MAY, 1990 ALCATEL N.V. I Ir I 4( 1 L,