AU606176B2 - Programmable balance filter arrangement - Google Patents

Description

4 606176 4 44 44 0 COMNW)1NWEALTH OF AUSTRALIA PATENTS ACT 1952-1969 COMI~rhETE SPECIFICATION FOR THE INVENTION ENTITLED 4 04 0 4 0

I

"1PROGRArVIABLE BALANCE FILTER ARRANGEMENT" The following statement is a full description of thia invention, including the best method of performing it known to us:- I' This invention relates to digitally implemented filters, and in particular, though not exclusively to programmable balance filters used to achieve trans-hybrid balancing for a range of subscriber line characteristics in primary multiplex telecommunication equipment.

A known readily available filter of the above type is an n-tap Finite Impulse Response (FIR) filter having eight programmable coefficients and a tap spacing of 62.5 u/s to which is applied a conventional iterative algo- Srithm such as, for example, the Least Mean Square (LMS) algorithm to adjust the filter coefficients to achieve optimum trans-hyb-id balancing.

t I 1 0 In some digital switching systems, however, digiLal processing is accomplished at a frame rate of 8 kHz thereby providing a digital output/input for transmission/reception every 125 u/s. If a FIR filter having taps spaced at 125 u/s is unavailable and it is necessary to use the aforementioned known FIR filter having taps spaced at 62.5 u/s (16 kHz), optimum trans-hybrid balancing cannot be achieved because the conventional Siterative algorithms will only balance the filter to an accuracy corresponding to the lower sampling frequency which may not meet specifications requir d by the telecommunication authority.

It is therefore an object of the present invention to provide a method of balancing a programmable balance filter wherein the clock rate at which the errors are sampled is not significant.

According to a first aspect of the invention there is provided a uithod of providing trans-hybrid balance for a range of line characteristics of a 2-wire line coupled to a 4-wire digital communication circuit comprising a send circuit and a receive circuit, raid coupling of the 2-wire line to the 4-wire communication circuit being facilitated by a programmable n-tap Finite Impulse Response filter means comprising n-tap coefficients, wherein the trans-hybrid balance of said filter is achieved by perturbing each tap coefficient positively by a predetermined value and then perturbing each coefficient negatively by a predetermined value, after 2 each perturbation a test pulse of a predetermined length is injected into said receiver circuit and an error signal produced by said test pulse is read by error measuring means coupled to said send circuit and stored in a memory means associated with a processor means, a gradient is calculated by said processor means for each coefficient until the magnitude of all gradients adjusts below a predetermined value stored in said processor.

According to a further aspect of the invention there is provided an arrangement compr .ing a 2-wire line coupled to a 4-wire digital communication circuit ,Lvjng a send circuit and a receive circuit, said coupling of the 2-wire line to the 4-wire digital communication circuit being facilitated by a programmable n-tap Finite Impulse Response filter means comi o prising n-tap coefficients, wherein said arrangement includes error measuring means selectively coupled to said send circuit, a test pulse generator means selectively coupled to said receive circuit, said error measuring means and said test pulse generator means being operatively associated with a processor means and a memory means, whereby trans-hybrid S"o balance of said filter for a range of line characteristics of said 2-wire o" line is achieved by perturbing each tap coefficient positively by a predetermined value and then perturbing each coefficient negatively by a prede- -termined value, and after each perturbation causing said test pulse 4 generator means to inject a test pulse of a predetermined length into said receiver circuit, an error signal produced by said test pulse being read by said error measuring means and stored in said memory means, said processor means calculating a gradient for each coefficient until the magnitude of all gradients adjusts below a predetermined value stored in said memory indicating optimum trans-hybrid balance.

In order that the invention may be readily carried into effect, embodiments thereof will now be described, in which: SPig. 1 shows an arrangement of a FIR filter; I- -;ra~.lrtr-uua~ Fig. 2 shows a block diagram of an arrangement incorporating ti, invention.

Referring to the drawing the FIR balance filter shown in 1ig. 1 comprises a filter input means coupled to seven cascaded digital registers Tl-T7. The input means together with the output of each register is provided with tap output means applied to eight multipliers X1-X8- Daring each cycle of the clock frequency at which the fil] operiates, tap coefficients b0-b8 are multiplied by the tap output and the results of the o multiplications are summed in summing means 2 to produce the filter output Si' signal at filter output 3 for that particular clock cycle.

Referring to Fig. 2, there is shown elements of multiplex equipment associated with a 30 channel PCM tPlecommunication system for combining voice frequency channels into a single 2048 Kbit/s digital stream. The el- V 0 0 0 ements consist of a Subscriber line Audio Processing Circuit (SLAC) 4 and a Signalling Control Unit (SCU) The SLAG 4 is a digital signal processing device which performs all coding, decoding and filtering functions for processing VF analogue signals o into Pulse Code Modulated (PCM) outputs via the Analogue/Digital converter 6, and processing PCM inputs into analogue outputs via the Digital/Analogue S 20 converter 7. The process is accomplished at a frame rate of 8 kHz and the digital output/input is available for transmission/reception every 125 u/s providing 32 8 bit channels per frame.

Further, SLAC 4 incorporates a hybrid balance arrangement to facilitate 2 wire to 4 wire conversion of the 2 wire subscriber line coupled to SLAG 4 via the 2 wire line interface The hybrid balance arrangement is in the form of an FIR balance filter 10 details of which are shown in Fig.

1, and a summing device 9. The balance filter forms a feedback path from the receive path to the transmit path, the summing device 9 performing a cancellation of the echo signal by summing the receive signal received via the balance filter and the receive signal from the transmit signal path.

The balance filter is coupled to and controlled by a central microprocessoL i 11 associated with the SCU 5 which is arranged to detect the configuration of each SLAC and thereby implement the correct signalling protocols.

Central microprocessor 11 implements the software algorithms required for channel scanning and processing of signalling protocols. Moreover, microprocessor 11 implements a hybrid balance algorithm to initially adapt the hybrid balance filter to match the associated VF circuit viz the subscriber line.

j The hybrid balance algorithm used is an iterative algorithm called a i0 perturbation algorithm a description of which is as follows: Making use of the following notation: the output signal from the SLAC is sampled over the integer m.

T is the system sampling period of 125 u/s.

b is the matrix of FIR filter tap coefficients applying during iter- "o ation k.

i and j are integers representing the coefficient to be perturbed.

i o i, J 7.

represents a positive perurb on represents a posinegative perturbation.

represents a negative perturbation.

L is the number of output samples measured.

I Let v(mT, be the output sequence obtained from the SLAC when the tap coefficient vector of the balance filter is set to b b k+ ej 1 th where ej is a vector which is all zero except for the j component which is 1 and Y is a positive constant, and the test sequence is applied. Note that merely states that bk has been perturbed by an .nount 8 only in its j component.

thA Similarly, let v(mT, bk, j, be the output sequence obtained from ~-k the SLAC when the tap coefficient vector of the balance filter is set to b b ej (2) Note that v(mT,bk,j,+) and v(mT,bk,j,-) are both sequences at 8KHz availi able at the output of the SLAC.

i It can be shown that the n components of the gradient g(bk) are given by: L Sg(b)] rL (v(mT,bk, i, v(mT,bk i (3) and 0 k bk g(b- (4) The hybrid balance perturbation algorithm is invoked by the operation of a "Train Hybrid" key (not shown) on the SCU. After selecting the channel whose hybrid is to be balanced, the "Train Hybrid" key is operated and o o S the following sequence of events occur: 4 49 S* i1. Microprocessor 11 causes all coefficient values in the Balance filter to be set to zero.

t 2. Filter coefficient bO is then "positively perturbed" by having a small predetermined value added to it by the microprocessor. (See equation 1).

3. The microprocessor causes a test pulse of 125 u/s to be injected in Timeslot 0.

4. The test pulse amplitude is distorted by reflections and echoes caused by the 2 wire line characteristic and by leakage of the test pulse signal from the "Rec" path 12 into the "Trans" path 13.

The distorted test pulse is returned on the "Trans" path to the microprocessor via the "Read Return Error" means 14.

6. The "Read Return Error" means reads the digital samples of the returned pulse and stores representation of those signals in the microprocessors memory (V[mT, 7. The first filter coefficient is returned to bO which is "negatively perturbed" by having a small predetermined value subtracted from it by the microprocessor (See equation 2).

8. The microprocessor causes the "Test Signal Generator" 15 to inject a second test pulse into the Time-slot 0 and steps 1 to 6 above are repeated so that digital samples of the "Trans" signals are read by the Read Return Error means and representations of those signals are stored in the microprocessor memory (V[mT,bk,j,

S

o 9. The first coefficient is restored to its orginal value of bO by the microprocessor.

10. An error gradient is calculated by the microprocessor based upon the two sets of readings stored in its memory (see equation 3) 11. Steps 1 to 10 are repeated a further seven times for perturbing the remaining 7 coefficients resulting in a total of 8 error gradients stored in the memory.

'Bo 12. The 8 error gradients are then utilized by the microprocessor to calculate 8 new coefficient values (see equation 4).

11 13. The first filter coefficient bO is "positively perturbed" by having the small predetermined value (see equation 1) added to it by the microprocessor and steps 3 to 12 above are repeated until the microprocessor determines the magnitude of the eight error gradients is below a predetermined value therefore indicating to the microprocessor that optimum balance has been accomplished.

14. The microprocessor returns the channel to normal operation and stores a copy of the determined coefficients in a non-volatile memory so that if the SLAG is replaced the previously determined coefficients apply.

A weighting element may be introduced which is calculated to envisage distortion of the test signal by characteristics of components in the filter.

7 M FM__, iplc--~rr~m~ In Fig. 2, 16 is the transmit amplifier, 17 is the receive amplifier 18 is a resistor, 20 is the two wire line, and 21 is the control line, 6 being an analog to digital converter and 7 being a digital to analog converter.

It can be seen that only the overall error is required to update each tap coefficient and thus time alignment of the errors and coefficient is not necessary. Consequently, the clock rate at which the errors are sampled is not significant.

t hi I i, S« i- i

Claims (9)

1. A method of providing trans-hybrid balance for a range of line characteristics of a 2-wire line coupled to a 4-wire digital communication circuit comprising a send circuit and a receive circuit, said coupling of the 2-wire line to the 4-wire communication circuit being facilitated by a programmable n-tap Finite Impulse Response filter means comprising n-tap coefficients, wherein the trans-hybrid balance of said filter is ach.eved by perturbing each tap coefficient positively by a predetermined value and thei perturbing each coefficient negatively by a predetermined value, after each perturbation a test pulse of a predetermined length is injected into 0 said receiver ciocuit and an error signal produced by said test pulse is read by error measuring means coupled to said send circuit and stored in a memory means associated with a processor means, a gradient is calculated by 0 said processor means for each coefficient until the magnitude of all gradi- ents adjusts below a predetermined value stored in said processor. 0

2. A method as claimed Jn claim 1, wherein the value by which each tap coefficient is perturbed positively and negatively is: b =bk dej and b= b -6eJ, respectively; where b is the matrix of the Finite Impulse Re- -k zk sponse filter tap co-efficients applying during iteration k, eid ej is a vector which is all zero except for the j th component Vhich is i, and Si6 a positive constant.

3. A method as claimed in claim 1 or 2, wherein said Finite Impulse Response filter means comprises n taps spaced at 62.5 u/s, and wherein sail digital communication circuit is arranged such that digital processing therein is accomplished at a frame rate of 8 kHz.

4. A method of providing trans-t. .,tiA balance, substantially as herein described with reference to Figs. 1 and 2 of the accompanying drawings.

An arrangement comprising a 2-wire line coupled to a 4-wire digital communication circuit having a send circuit ald a receive circuit, said coupling of the 2-wire line to the 4-wire digital communication circuit be- ing facilitated by a programmable n-tap Finite Impulse Response filter means comprising n-tap coefficients, wherein said arrangement includes er- ror measuring means selectively coupled to said send circuit, a test pulse generator means selectively coupled uo said receive circuit, said error measuring means and said test pulse generator means being operatively asso- ciated with a processor means and a memory means, whereby trans-hybrid bal- ance of said filter for a range of line characteristics of said 2-wire line is achieved by perturbing each tap coefficient positively by a predeter- mined value and then perturbing each coefficient negatively by a predeter- mined value, and after each perturbation causing said test pulse generator means to inject a test pulse of a predetermined length into said receiver o circuit, an error signal produced by said test pulse being read by said er- o ot ror measuring means and stored in said memory means, said processor means calculating a gradient for each coefficient until the magnitude of all gra- dients adjusts below a predetermined value stored in said memory indicating optimum trans-hybrid balance. 0

6. An arrangement as claimed in claim 5, wherein the value by which each tap coefficient is perturbed positively and negatively is: b bk Sej and b bk ej respectively where b is the matrix of the Finite Im- pulse Response filter tap coefficients applying during iteration k, and ej IH is a vector which is all zero except for the jth component which is 1; and i is a positive constant.

7. An arrangement as claimed in claim 5 or 6, wherein said Finite Im- J/ pulse Responae filter means comprises n-taps spaced at 62.5 u/s, and wherein saiJ digital communication circuit is arranged such that digital processing is accomplished therein at a frame rate of 8kHz.

8. An arrangement as claimed in claim 7, wherein said test pulse is a single sample impuls of 125 u/s length.

9. An arrangement substantially as herein described with reference to Figs. 1 and 2 of the accompanying drawings. An arrangemnent as claimed in any one of claims 5 to 9, associated With a3chnePusCoeMdltdtelecom On system, DATED THIS THIRTIETH DAY OF JUNE, 1988 STANDARD TELEPHONES AND CABLES PTY. LIMITED