AU5929998A - Modified reed-solomon error correction system using (w+i+1)-bit representations of symbols of gf(2w+i) - Google Patents

Modified reed-solomon error correction system using (w+i+1)-bit representations of symbols of gf(2w+i)

Info

Publication number
AU5929998A
AU5929998A AU59299/98A AU5929998A AU5929998A AU 5929998 A AU5929998 A AU 5929998A AU 59299/98 A AU59299/98 A AU 59299/98A AU 5929998 A AU5929998 A AU 5929998A AU 5929998 A AU5929998 A AU 5929998A
Authority
AU
Australia
Prior art keywords
symbols
error correction
correction system
solomon error
bit representations
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
AU59299/98A
Other languages
English (en)
Inventor
Shih Mo
Ba-Zhong Shen
Lih-Jyh Weng
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Quantum Corp
Original Assignee
Quantum Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Quantum Corp filed Critical Quantum Corp
Publication of AU5929998A publication Critical patent/AU5929998A/en
Abandoned legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/13—Linear codes
    • H03M13/15—Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes
    • H03M13/151—Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes using error location or error correction polynomials

Landscapes

  • Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Algebra (AREA)
  • General Physics & Mathematics (AREA)
  • Pure & Applied Mathematics (AREA)
  • Probability & Statistics with Applications (AREA)
  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Error Detection And Correction (AREA)
  • Detection And Correction Of Errors (AREA)
AU59299/98A 1997-01-23 1998-01-23 Modified reed-solomon error correction system using (w+i+1)-bit representations of symbols of gf(2w+i) Abandoned AU5929998A (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US08786894 1997-01-23
US08/786,894 US5948117A (en) 1997-01-23 1997-01-23 Modified Reed-Solomon error correction system using (W+i+1)-bit representations of symbols of GF(2w+i)
PCT/US1998/001356 WO1998035451A1 (en) 1997-01-23 1998-01-23 MODIFIED REED-SOLOMON ERROR CORRECTION SYSTEM USING (w+i+1)-BIT REPRESENTATIONS OF SYMBOLS OF GF(2w+i)

Publications (1)

Publication Number Publication Date
AU5929998A true AU5929998A (en) 1998-08-26

Family

ID=25139882

Family Applications (1)

Application Number Title Priority Date Filing Date
AU59299/98A Abandoned AU5929998A (en) 1997-01-23 1998-01-23 Modified reed-solomon error correction system using (w+i+1)-bit representations of symbols of gf(2w+i)

Country Status (5)

Country Link
US (1) US5948117A (enExample)
EP (1) EP0906665A4 (enExample)
JP (1) JP3989558B2 (enExample)
AU (1) AU5929998A (enExample)
WO (1) WO1998035451A1 (enExample)

Families Citing this family (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5889794A (en) * 1997-09-30 1999-03-30 Quantum Corporation Two-level error correction encoder
JP4088998B2 (ja) 1998-02-16 2008-05-21 ソニー株式会社 光ディスクの記録／再生方法、光ディスク及び光ディスク装置
US6148430A (en) * 1998-05-15 2000-11-14 Quantum Corporation Encoding apparatus for RAID-6 system and tape drives
JP3272317B2 (ja) * 1999-01-21 2002-04-08 インターナショナル・ビジネス・マシーンズ・コーポレーション 誤り検出装置およびその方法
US6360348B1 (en) * 1999-08-27 2002-03-19 Motorola, Inc. Method and apparatus for coding and decoding data
US6701336B1 (en) 1999-11-12 2004-03-02 Maxtor Corporation Shared galois field multiplier
US6779014B1 (en) * 2001-02-15 2004-08-17 Chung-Shan Institute Of Science & Technology Cyclic step by step decoding method used in discrete fourier transform cyclic code of a communication system
CN100399463C (zh) * 2002-09-24 2008-07-02 联发科技股份有限公司 数字激光视盘机的检错码检查装置与检查方法
US7162679B2 (en) * 2003-12-12 2007-01-09 Analog Devices, Inc. Methods and apparatus for coding and decoding data using Reed-Solomon codes
US7426676B2 (en) * 2004-01-14 2008-09-16 Broadcom Corporation Data retrieval from a storage device using a combined error correction and detection approach
US7228490B2 (en) * 2004-02-19 2007-06-05 Quantum Corporation Error correction decoder using cells with partial syndrome generation
TWI292866B (en) * 2005-09-09 2008-01-21 Via Tech Inc Method for calculatng an error detection code
US8286059B1 (en) 2007-01-08 2012-10-09 Marvell International Ltd. Word-serial cyclic code encoder
KR101437396B1 (ko) * 2008-02-27 2014-09-05 삼성전자주식회사 레이턴시를 줄일 수 있는 에러 정정 블록을 포함하는메모리 시스템 및 그것의 에러 정정 방법
US8365053B2 (en) * 2009-05-27 2013-01-29 International Business Machines Corporation Encoding and decoding data using store and exclusive or operations
US8607129B2 (en) * 2011-07-01 2013-12-10 Intel Corporation Efficient and scalable cyclic redundancy check circuit using Galois-field arithmetic
US8839083B2 (en) * 2011-10-25 2014-09-16 Taejin Info Tech Co., Ltd. Secure error detection and synchronous data tagging for high-speed data transfer
TWI742371B (zh) * 2019-05-13 2021-10-11 義守大學 應用單項跡之錯誤更正方法

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4413339A (en) * 1981-06-24 1983-11-01 Digital Equipment Corporation Multiple error detecting and correcting system employing Reed-Solomon codes
US4856003A (en) * 1987-05-07 1989-08-08 Digital Equipment Corporation Error correction code encoder

Also Published As

Publication number Publication date
JP2000507434A (ja) 2000-06-13
JP3989558B2 (ja) 2007-10-10
US5948117A (en) 1999-09-07
EP0906665A4 (en) 2000-11-15
EP0906665A1 (en) 1999-04-07
WO1998035451A1 (en) 1998-08-13

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