AU5777601A - Semiconductor device with an improved lead-chip adhesion structure and lead frame to be used therefor - Google Patents

Semiconductor device with an improved lead-chip adhesion structure and lead frame to be used therefor Download PDF

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Publication number
AU5777601A
AU5777601A AU57776/01A AU5777601A AU5777601A AU 5777601 A AU5777601 A AU 5777601A AU 57776/01 A AU57776/01 A AU 57776/01A AU 5777601 A AU5777601 A AU 5777601A AU 5777601 A AU5777601 A AU 5777601A
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AU
Australia
Prior art keywords
electrically insulative
insulative adhesive
adhesive tape
semiconductor chip
inner leads
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
AU57776/01A
Inventor
Michihiko Ichinose
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NEC Electronics Corp
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NEC Corp
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Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to AU57776/01A priority Critical patent/AU5777601A/en
Publication of AU5777601A publication Critical patent/AU5777601A/en
Assigned to NEC ELECTRONICS CORPORATION reassignment NEC ELECTRONICS CORPORATION Alteration of Name(s) of Applicant(s) under S113 Assignors: NEC CORPORATION
Abandoned legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/4826—Connecting between the body and an opposite side of the item with respect to the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49175—Parallel arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Lead Frames For Integrated Circuits (AREA)

Description

S&F Ref: 424400D1
AUSTRALIA
PATENTS ACT 1990 COMPLETE SPECIFICATION FOR A STANDARD PATENT
ORIGINAL
Name and Address of Applicant: Actual Inventor(s): Address for Service: NEC Corporation 7-1, Shiba Minato-ku Tokyo Japan Michihiko Ichinose Spruson Ferguson St Martins Tower,Level 31 Market Street Sydney NSW 2000 (CCN 3710000177) Invention Title: Semiconductor Device with an Improved Lead-chip Adhesion Structure and Lead Frame to be Used Therefor C The following statement is a full description of this invention, including the best method of performing it known to me/us:- 5845c Pf-2090/nec/Australia/mh SEMICONDUCTOR DEVICE WITH AN IMPROVED LEAD-CHIP ADHESION STRUCTURE AND LEAD FRAME TO BE USED THEREFOR BACKGROUND OF THE INVENTION 5 The present invention relates to a semiconductor device with an improved lead-hip adhesion structure and a lead frame, and more particularly to a semiconductor device with a lead-on-chip structure and a lead frame to be used therefor.
FIG. 1 is a fragmentary cross sectional elevation view illustrative to of a conventional lead-on-chip structure of a semiconductor device. Inner leads 1 extend over a top surface of a semiconductor chip 4 The inner ."leads 1 have stitch portions 2 at inside edges thereof. Ai" insulative adhesive tape 3 is adhered with bottom surfaces of the stitch portions 2 of the inner leads 1 aligned in the left side. Another insulative adhesive tape 3 15. is adhered with bottom surfaces of the stitch portions 2 of the,iiner leads 1 aligned in the right side. Each of the insulative adhesive tape'S 3 has both surfaces on which an insulative adhesive agent has been applied.
Alternatively, each of the insulative adhesive tapes 3 has both surfaces on which adhesive layers have been formed. The inner leads 1 extend toward a 2o center line of the semiconductor chip 4. The semiconductor chip 4 is bonded or adhered with the bottom surfaces of the insulative adhesive tapes 3, wherein the insulative adhesive tapes 3 have already been adhered to the bottom surfaces of the stitch portions 2 of the inner leads 1. The semiconductor chip 4 has two alignments of bonding pads 10 along the center line so that individual bonding pads correspond to individual inner Page 1 Pf-2090/nec/Australia/mh leads 1 as illustrated in FIG. 2. The two alignments of bonding pads 10 of the semiconductor chip 4 are positioned inside of the stitch portions 2 of the inner leads 1 and also the insulative adhesive tapes 3. The stitch portion 2 of the inner lead 1 is bonded through a bonding wire 5 to the corresponding bonding pad 10 formed on the semiconductor chip 4 so that the inner leads 1 are electrically connected through the bonding wires 5 to the corresponding bonding pads 10 formed on the semiconductor chip 4.
FIG. 3 is a fragmentary cross sectional elevation view illustrative of the above conventional lead-on-chip structure of the semiconductor to device, wherein inner leads are in contact with edges of the semiconductor chip 4 to describe a first problem with the above conventional lead-on-chip structure. As shown in FIG. 3, the inner leads 1 are fixed at the stitch portions 2 by the insulative adhesive tapes 3 but other portions of the inner leads 1 positioned outside of the stitch portions 2 are not fixed. The 1i- semiconductor chip 4 is mounted on a printed circuit board by use of a sealing resin wherein a heat is applied to the semiconductor chip 4 and the inner leads 1. The insulative adhesive tapes 3 have a different thermal expansion coefficient from that of the sealing resin, for which reason a stress is generated by the difference in thermal expansion coefficient 20 between the insulative adhesive tapes 3 and the sealing resin. The stress is applied between the insulative adhesive tapes 3 and the sealing resin, whereby a pealing may be generated between the insulative adhesive tapes S'3 and the sealing resin. In order to avoid this problem with pealing between the insulative adhesive tapes 3 and the sealing resin, it is effective to 2s- narrow the width of the insulative adhesive tapes 3 as much as possible. In the above viewpoints, it is preferable that a pair of possible slender insulative adhesive tapes 3 are provided so that when the semiconductor I chip 4 has been bonded to the bottom surfaces of the insulative adhesive tapes 3, the possible slender insulative adhesive tapes 3 are positioned along the two alignments of the bonding pads 10 formed on the semiconductor chip 4 as closely to the two alignments of the bonding pads so as to shorten the length of the individual bonding wires 10. The long bonding wires have a problem with unstability in shape thereof and also is likely to be deformed by a flow of molten sealing resin when the sealing 31 resin is injected thereunto. For those reasons, it is preferable to shorten the length of the bonding wire 10. This requires that the stitch portion 2 of the a Page 2 Pf-2090/nec/Australia/mh inner lead 1 is positioned as closely to the bonding pad 10 provided close to the center line of the semiconductor chip 4 as possible. This results in that a long part of the inner lead 1 positioned outside of the stitch portion 2 extends over the semiconductor chip 4. This is remarkable as the size of the 6- semiconductor chip 4 becomes large. The long part of the inner lead 1 positioned outside of the stitch portion 2 is not fixed by the insulative adhesive tapes 3. Namely, the long inner lead 1 extending over the semiconductor chip 4 is fixed only at the stitch portion 2 thereof by the slender insulative adhesive tape 3. For those reasons, even if a slight deformation appears to such the inner lead 1 when the sealing resin is injected, the inner lead 1 might be made into contact with the edge of the semiconductor chip 4. The likelihood of contact between the inner lead 1 and the edge of the semiconductor chip 4 is high as the size of the semiconductor chip 4 is large.
The above conventional lead-on-chip structure of the semiconductor device is further engaged with a second problem with likelihood of exposure of the tops of the bonding wires 5 or the bottom surface of the semiconductor chip 4 from the sealing resin even after the semiconductor device has been packaged with the sealing resin. As 20 described above, the long part of the individual inner lead 1 extends over the semiconductor chip 4 and is not fixed by the slender insulative adhesive tape 3. This allows the semiconductor chip 4 to move or displace in a direction vertical to the surface of the semiconductor chip 4 by the pressure of the sealing resin injected into dies for molding the semiconductor device.
25 FIG. 4A is a fragmentary cross sectional elevation view illustrative of a *semiconductor package, wherein the semiconductor chip 4 has been moved upwardly by the pressure of the sealing resin injected into the dies and the .i tops of the bonding wires 5 are shown from the sealing resin. FIG. 4B is a fragmentary cross sectional elevation view illustrative of a semiconductor package, wherein the semiconductor chip 4 has been moved downwardly by the pressure of the sealing resin injected into the dies and the bottom surface of the semiconductor chip 4 is shown from the sealing resin. Once either the top of the bonding wire 5 or the bottom of the semiconductor chip 4 is exposed from the sealing resin as illustrated in FIG. 4A or 4B, then a reliability of packaging is remarkably deteriorated and it may no longer be possible to use such the semiconductor package. Namely, the Page 3 Pf-2090/nec/Australia/mh above conventional lead-on-chip structure may result in remarkable drop of the yield of the products.
In order to avoid the above problem with movement of the semiconductor chip 4 by pressure of the molten resin injected into the dies, it is required to select an optimum condition for injection of the resin into the dies. Actually, however, the available ranges of the condition for the injection such as injection speed are extremely narrow. Determination of the available ranges of the condition for the injection is time consuming and complicated procedures. Further, the available ranges of the condition /o for the injection are changed even by a slight variation in lot of the resin.
This means it required to newly set or determine the optimum condition or extremely narrow available range even when the lot of the resin is changed.
The above lead-on-chip structure is also engaged with the following third problem. Even if the tops of the bonding wires 5 or the bottom of the semiconductor chip 4 are not exposed from the sealing resin, movement or shift in vertical direction to the surface of the semiconductor chip 4 results in variation in thickness of the resin from predetermined thicknesses. A balance is lost in thickness between an upper portion of the resin overlying the semiconductor chip 4 and a lower portion of the resin 2o underlying the semiconductor chip 4. As a result, the semiconductor package may be bent or arched. Further, a reduction in thickness of the upper or lower portion of the resin results in a drop of strength. If a stress is concentrated into the thickness-reduced portion of the resin, a crack is likely to appear on the thickness-reduced portion of the resin.
S. zs- In addition to the above lead-on-chip structure of the semiconductor device, the subsequent description will focus on a chip-onlead structure of the semiconductor device. FIG. 5A is a fragmentary cross sectional elevation view illustrative of a conventional chip-on-lead structure of a semiconductor device. Inner leads 1 extend under a bottom So surface of a semiconductor chip 4. The inner leads 1 have stitch portions 2 at inside edges thereof. An insulative adhesive tape 3 is adhered with top surfaces of the stitch portions 2 of the inner leads 1 aligned in the left side.
Another insulative adhesive tape 3 is adhered with top surfaces of the stitch portions 2 of the inner leads 1 aligned in the right side. Each of the insulative adhesive tapes 3 has both surfaces on which an insulative adhesive agent has been applied. Alternatively, each of the insulative Page 4 Pf-2090/nec/Australia/mh adhesive tapes 3 has both surfaces on which adhesive layers have been formed. The inner leads 1 extend toward a center line of the semiconductor chip 4. The semiconductor chip 4 is bonded or adhered with the top surfaces of the insulative adhesive tapes 3, wherein the insulative adhesive s tapes 3 have already been adhered to the top surfaces of the stitch portions 2 of the inner leads 1. The semiconductor chip 4 has two alignments of bonding pads 10 along opposite sides of the semiconductor chip 4 so that individual bonding pads 10 correspond to individual inner leads 1. The stitch portion 2 of the inner lead 1 is bonded through a bonding wire 5 to Io the corresponding bonding pad 10 formed on the top surface of the semiconductor chip 4 so that the inner leads 1 are electrically connected through the bonding wires 5 to the corresponding bonding pads FIG. 5B is a fragmentary cross sectional elevation view illustrative of the above conventional lead-on-chip structure of the Is semiconductor device, wherein inner leads 1 are in contact with edges of the semiconductor chip 4 to describe the same problem as engaged with the above conventional lead-on-chip structure. As shown in FIG. 5B, the inner leads 1 are fixed at the stitch portions 2 by the insulative adhesive tapes 3 i" but other portions of the inner leads 1 positioned outside of the stitch portions 2 are not fixed. The semiconductor chip 4 is mounted on a printed circuit board by use of a sealing resin wherein a heat is applied to the semiconductor chip 4 and the inner leads 1. The insulative adhesive tapes 3 S. have a different thermal expansion coefficient from that of the sealing resin, for which reason a stress is generated by the difference in thermal 2,s expansion coefficient between the insulative adhesive tapes 3 and the sealing resin. The stress is applied between the insulative adhesive tapes 3 and the sealing resin, whereby a pealing may be generated between the :insulative adhesive tapes 3 and the sealing resin. In order to avoid this problem with pealing between the insulative adhesive tapes 3 and the sealing resin, it is effective to narrow the width of the insulative adhesive tapes 3 as much as possible. In the above viewpoints, it is preferable that a pair of possible slender insulative adhesive tapes 3 are provided so that when the semiconductor chip 4 has been bonded to the bottom surfaces of the insulative adhesive tapes 3, the possible slender insulative adhesive 3S tapes 3 are positioned relatively close to the center line of the semiconductor chip 4. This results in that a long part of the inner lead 1 nA Page Pf-2090/nec/Australia/mh positioned outside of the stitch portion 2 extends over the semiconductor chip 4. This is remarkable as the size of the semiconductor chip 4 becomes large. The long part of the inner lead 1 positioned outside of the stitch portion 2 is not fixed by the insulative adhesive tapes 3. Namely, the long 6 inner lead 1 extending over the semiconductor chip 4 is fixed only at the stitch portion 2 thereof by the slender insulative adhesive tape 3. For those reasons, even if a slight deformation appears to such the inner lead 1 when the sealing resin is injected, the inner lead 1 might be made into contact with the edge of the semiconductor chip 4. The likelihood of contact lo between the inner lead 1 and the edge of the semiconductor chip 4 is high as the size of the semiconductor chip 4 is large.
The above conventional lead-on-chip structure of the semiconductor device is further engaged with a second problem with likelihood of exposure of the tops of the bonding wires 5 or the bottom surface of the stitched portion 2 of the inner lead 1 from the sealing resin even after the semiconductor device has been packaged with the sealing resin. As described above, the long part of the individual inner lead 1 extends under the semiconductor chip 4 and is not fixed by the slender insulative adhesive tape 3. This allows the semiconductor chip 4 to move or 2o displace in a direction vertical to the surface of the semiconductor chip 4 by the- pressure of the sealing resin injected into dies for molding the semiconductor device. Once either the top of the bonding wire 5 or the S"bottom of the stitched portion 2 of the inner lead 1 is exposed from the sealing resin, then a reliability of packaging is remarkably deteriorated and 2,5 it may no longer be possible to use such the semiconductor package.
Namely, the above conventional lead-on-chip structure may result in remarkable drop of the yield of the products.
In order to avoid the above problem with movement of the semiconductor chip 4 by pressure of the molten resin injected into the dies, 32o it is required to select an optimum condition for injection of the resin into the dies. Actually, however, the available ranges of the conditions for the injection such as injection speed are extremely narrow. Determination of the. available ranges of the condition for the injection is time consuming and complicated procedures. Further, the available ranges of the condition 3r for the injection are changed even by a slight variation in lot of the resin.
This means it required to newly set or determine the optimum condition or Page 6 extremely narrow available range even when the lot of the resin is changed.
The above chip-on-lead structure is also engaged with the following third problem. Even if the tops of the bonding wires 5 or the bottom of the stitched portions 2 of the inner leads 1 are not exposed from S the sealing resin, movement or shift in vertical direction to the surface of the semiconductor chip 4 results in variation in thickness of the resin from predetermined thicknesses. A balance is lost in thickness between an upper portion of the resin overlying the semiconductor chip 4 and a lower portion of the resin underlying the semiconductor chip 4. As a result, the '0 semiconductor package may be bent or arched. Further, a reduction in thickness of the upper or lower portion of the resin results in a drop of strength. If a stress is concentrated into the thickness-reduced portion of the resin, a crack is likely to appear on the thickness-reduced portion of the resin.
In the above circumstances, it had been required to develop a novel lead-on-chip structure of a semiconductor device free from the above problems and a lead frame to be used therefor, in addition a novel chip-onlead structure of a semiconductor device free from the above problems and a lead frame to be used therefor.
Accordingly, a need exists to provide a novel lead-on-chip structure of a o* semiconductor device free from the above problems.
A- further need exists to provide a novel lead-on-chip structure of a semiconductor device, which is capable of preventing any contact between-n inner lead and an edge portion of a semiconductor chip.
2S- A still further need exists to provide a novel lead-on-chip structure of a semiconductor device, which is capable of keeping a constant distance between a semiconductor chip and an inner lead extending over the semiconductor chip.
Yet a further need exists to provide a novel lead-on-chip structure of a semiconductor device, which is capable of preventing any substantive movement or shift in a direction vertical to the surface of the semiconductor chip by pressure of a molten resin injected into dies for packaging the semiconductor device.
A further need exists to provide a novel lead-on-chip structure of a semiconductor device, which is capable of preventing exposure of tops of bonding wires Page 7 by substantive movement or shift in a direction vertical to the surface of the semiconductor chip by pressure of a molten resin injected into dies for packaging the semiconductor device.
A further need exists to provide a novel lead-on-chip structure of a s semiconductor device, which is capable of preventing a substantive loss of a balance in thickness between upper and lower portions of a sealing resin packaging a semiconductor chip by substantive movement or shift in a direction vertical to the surface of the semiconductor chip by pressure of a molten resin injected into dies for packaging the semiconductor device.
A need also exists to provide a novel lead-on-chip structure of a semiconductor device, which is capable of preventing appearance of crack on a thickness-reduced portion of a resin due to a substantive loss of a balance in thickness between upper and lower portions of a sealing resin packaging a semiconductor chip by substantive movement of shift in a direction vertical to the surface of the semiconductor chip by pressure ofa molten resin injected into dies for packaging the semiconductor device.
i' "Another need exists to provide a novel lead-on-chip structure of a semiconductor device which allows a high yield of manufacturing.
Still another need exists to provide a novel lead-on-chip structure of a S•semiconductor device which has a high reliability.
Yet another need exists to provide a novel lead frame for a lead-on-chip structured semiconductor device free from the above problems.
A need exists to provide a novel lead frame for a lead-on-chip structured semiconductor device, which is capable of preventing any contact betweef~an inner lead *and an edge portion of a semiconductor chip.
An additional need exists to provide a novel lead frame for a lead-on-chip structured semiconductor device, which is capable of keeping a constant distance between •a semiconductor chip and an inner lead extending over the semiconductor chip.
A still additional need exists to provide a novel lead frame for a lead-on-chip structured semiconductor device, which is capable of preventing any substantive movement or shift in a direction vertical to the surface of the semiconductor chip by pressure of a molten resin injected into dies for packaging the semiconductor device.
Yet an additional need exists to provide a novel lead frame for a lead-on-chip structured semiconductor device, which is capable of preventing exposure of tops of bonding wires by substantive movement or shift in a direction vertical to the surface of [I:DaLUb\11BQJ838.doc:edg the semiconductor chip by pressure of a molten resin injected into dies for packaging the semiconductor device.
A further need exists to provide a novel lead frame for a lead-on-chip structured semiconductor device, which is capable of preventing a substantive loss of a balance in thickness between upper and lower portions of a sealing resin packaging a semiconductor chip by substantive movement or shift in a direction vertical to the surface of the semiconductor chip by pressure of a molten resin injected into dies for packaging the semiconductor device.
An additional need exists to provide a novel lead frame for a lead-on-chip structure semiconductor device, which is capable of preventing appearance of crack on a thickness-reduced portion of a resin due to a substantive loss of a balance in thickness between upper and lower portions of a sealing resin packaging a semiconductor chip by substantive movement or shift in a direction vertical to the surface of the semiconductor chip by pressure of a molten resin injected into dies for packaging the semiconductor I15 device.
ia...
A need also exists to provide a novel lead frame for a lead-on-chip structured semiconductor device which allows a high yield of manufacturing.
oo. An additional need exists to provide a novel lead-on-chip structure of a semiconductor device which has a high reliability.
A need also exists to provide a novel chip-on-lead structure of a semiconductor device free from the above problems.
A need also exists to provide a novel chip-on-lead structure of a "eniconductor S-device, which is capable of preventing any contact between an inner lea and an edge portion of a semiconductor chip.
A need also exists to provide a novel chip-on-lead structure of a semiconductor °device, which is capable of keeping a constant distance between a semiconductor chip and an inner lead extending over the semiconductor chip.
A need also exists to provide a novel chip-on-lead structure of a semiconductor device, which is capable of preventing any substantive movement or shift in a direction vertical to the surface of the semiconductor chip by pressure of a molten resin injected into dies for packaging the semiconductor device.
A need also exists to provide a novel chip-on-lead structure of a semiconductor device, which is capable of preventing exposure of tops of bonding wires by substantive movement or shift in a direction vertical to the surface of the semiconductor chip by pressure of a molten resin injected into dies for packaging the semiconductor device.
[I:%DayLb\ULIBQ]838 .do:edg:d A need also exists to provide a novel chip-on-lead structure of a semiconductor device, which is capable of preventing a substantive loss of a balance in thickness between upper and lower portions of a sealing resin packaging a semiconductor chip by substantive movement of shift in a direction vertical to the surface of the semiconductor chip by pressure of a molten resin injected into dies for packaging the semiconductor device.
A need also exists to provide a novel chip-on-lead structure of a semiconductor device, which is capable of preventing appearance of crack on a thickness-reduced portion of a resin due to a substantive loss of a balance in thickness between upper and lower portions of a sealing resin packaging a semiconductor chip by substantive movement or shift in a direction vertical to the surface of the semiconductor chip by pressure of a molten resin injected into dies for packaging the semiconductor device.
A need also exists to provide a novel chip-on-lead structure of a semiconductor device which allows a high yield of manufacturing.
s15 A need also exists to provide a novel chip-on-lead structure of a semiconductor •.device which has a high reliability.
A need also exists to provide a novel lead frame for a chip-on-lead structured "'"°"semiconductor device free from the above problems.
~A need also exists to provide a novel lead frame for a chip-on-lead structured S 20 semiconductor device, which is capable of preventing any contact between an inner lead and an edge portion ofa semiconductor chip.
A need also exists to provide a novel lead frame for a chip-on-lead structured semiconductor device, which is capable of keeping a constant distanie between a semiconductor chip and an inner lead extending over the semiconductor chip.
A need also exists to provide a novel lead frame for a chip-on-lead structured a semiconductor device, which is capable of preventing any substantive movement or shift in a direction vertical to the surface of the semiconductor chip by pressure of a molten resin injected into dies for packaging the semiconductor device.
A need also exists to provide a novel lead frame for a chip-on-lead structured semiconductor device, which is capable of preventing exposure of tops of bonding wires by substantive movement or shift in a direction vertical to the surface of the semiconductor chip by pressure of a molten resin injected into dies for packaging the semiconductor device.
A need also exists to provide a novel lead frame for a chip-on-lead structured semiconductor device, which is capable of preventing a substantive loss of.a balance in [I:\DayLib\UBQ]s838.doc:edg P I tt -11 thickness between upper and lower portions of a sealing resin packaging a semiconductor chip by substantive movement or shift in a direction vertical to the surface of the semiconductor chip by pressure of a molten resin injected into dies for packaging the semiconductor device.
A need also exists to provide a novel lead frame for a chip-on-lead structured semiconductor device, which is capable of preventing appearance of crack on a thicknessreduced portion of a resin due to a substantive loss of a balance in thickness between upper and lower portions of a sealing resin packaging a semiconductor chip by substantive movement or shift in a direction vertical to the surface of the semiconductor chip by pressure of a molten resin injected into dies for packaging the semiconductor device.
A need also exists to provide a novel lead frame for a chip-on-lead structured semiconductor device which allows a high yield of manufacturing.
A need also exists to provide a novel chip-on-lead structure of a semiconductor S 15s device which has a high reliability.
S:'""SUMMARY OF THE INVENTION oooAccording to a first aspect of the present invention, there is provided an adhering structure between a semiconductor chip and two alignments of first side inner leads and 20 second side inner leads extending in first and second sides of said semiconductor chip ooooo respectively, each of said first and second side inner leads having a stitched portion, said first and second sides being separated by a center line of said seimiconductor chip, said semiconductor chip and said first and second side inner leads being adhered to each other by first and second side electrically insulative adhesive tapes respectively, each of said first and second side electrically insulative adhesive tapes having both surfaces with adhesion force, said first and second side electrically insulative adhesive tapes extending on first and second inner stripe regions so as to adhere said stitched portions of said first and second side inner leads respectively, wherein each of said first and second side electrically insulative adhesive tapes is further present in at least two portions which are spaced from each other in a direction parallel to said center line and which are also located in the vicinity of an edge of said semiconductor chip, where said edge extends substantially in parallel to said center line, so that said inner leads, which extend through said two positions, are also fixed in the vicinity of said edge of said semiconductor chip.
[R:\LIBQ]996.doc:edg -12- According to a further aspect of the present invention, there is provided an electrically insulative adhesive tape structure to be used for adhering a semiconductor chip with inner leads extending substantially in parallel to each other and being aligned in a direction substantially in parallel to an edge of said semiconductor chip, each of said inner leads having an inside portion, said semiconductor chip and said inner leads being adhered to each other by said electrically insulative adhesive tape, said electrically insulative adhesive tape having both surfaces with adhesion force, said electrically insulative adhesive tape extending on an inner stripe region so as to adhere said inside portions of said inner leads, l0 wherein said electrically insulative adhesive tape is further present in at least two positions which are spaced from each other in a direction parallel to said edge of said semiconductor chip and which are also located in the vicinity of said edge of said semiconductor chip so that said inner leads, which extend through said two positions, are also adhered in the vicinity of said edge of said semiconductor chip.
15 According to a further aspect of the present invention, there is provided an i electrically insulative adhesive tape extending over stitched portions of inner leads of a lead frame, said inner leads extending substantially in parallel to each other and being i aligned in a direction substantially vertical to a longitudinal direction of said inner leads, so that said electrically insulative adhesive tape extends on an inner stripe region over said inner leads so as to adhere said stitched portions of said inner leads, and said °electrically insulative adhesive tape having both surfaces with adhesive force, wherein said electrically insulative adhesive tape is further present in at least two positions which are spaced from each other in a direction vertical to said longitudinal direction of said inner leads and which are also located outside of said stitched portions of said inner leads and said two portions are located in the vicinity of chip edge ""correspondence positions of said inner leads, where said chip edge correspondence *o position is previously determined to correspond to an edge of said semiconductor chip after said semiconductor chip has been adhered to said lead frame by said first and second electrically insulative adhesive tapes.
The above and other objects, features and advantages of the present invention will be apparent from the following descriptions.
The next page is page 14 [R:\LIBQ]996.doc:edg BRIEF DESCRIPTION OF THE DRAWINGS Preferred embodiments according to the present invention will be described in detail with reference to the accompanying drawings.
FIG. 1 is a fragmentary cross sectional elevation view illustrative of a conventional lead-on-chip structure of a semiconductor device.
FIG. 2 is a schematic plane view illustrative of a semiconductor chip on which a pair of slender stripe adhesive tapes are provided along just opposite outsides of two alignments of bonding pads provided on the semiconductor chip.
o l FIG. 3 is a fragmentary cross sectional elevation view illustrative of the above conventional lead-on-chip structure of the semiconductor chip to describe the first problem with the above conventional lead-on-chip e s tructure.
15 FG. 4A is a fragmentary cross sectional elevation view S illustrative of a semiconductor package, wherein the semiconductor chip has been moved upwardly by the pressure of the sealing resin injected into the dies and the tops of the bonding wires are shown from the sealing resin.
FIG. 4B is a fragmentary cross sectional elevation view 2- illustrative of a semiconductor package, wherein the semiconductor chip has been moved downwardly by the pressure of the sealing resin injected into the dies and the bottom surface of the semiconductor chip is shown from, the sealing resin.
FIG. 5A is a fragmentary cross sectional elevation view S. 7 illustrative of a conventional chip-on-lead structure of the semiconductor device.
FIG. 5B is a fragmentary cross sectional elevation view illustrative of the above conventional lead-on-chip structure of the semiconductor device, wherein inner leads are in contact with edges of the Page 14 Pf-2090/nec/Australia/mh semiconductor chip to describe the same problem as engaged with the above conventional lead-on-chip structure.
FIG. 6 is a fragmentary plane view illustrative of a novel leadon-chip structure of a semiconductor device in a first embodiment in 6- accordance with the present invention.
FIG. 7 is a fragmentary cross sectional elevation view illustrative of a novel lead-on-chip structure of a semiconductor device in a first embodiment in accordance with the present invention.
FIG. 8 is a fragmentary cross sectional elevation view illustrative of a novel lead-on-chip structure semiconductor device packaged with a sealing resin wherein a semiconductor chip had received up-force by a molten resin when the resin was injected into dies in a first embodiment in accordance with the present invention.
FIG. 9 is a fragmentary cross sectional elevation view illustrative 6- of a novel lead-on-chip structure semiconductor device packaged with a sealing resin wherein a semiconductor chip had received down-force by a molten resin when the resin was injected into dies in a first embodiment in accordance with the present invention.
FIG. 10 is a fragmentary cross sectional elevation view 20 illustrative of an electrically insulative adhesive tape to be used for adhering a semiconductor chip to inner leads in accordance with the present invention.
S"FIG. 11 is a fragmentary plane view illustrative of a novel leadon-chip structure of a semiconductor device in a second embodiment in 2t accordance with the present invention.
FIG. 12 is a fragmentary plane view illustrative of a novel leadon-chip structure of a semiconductor device in a third embodiment in accordance with the present invention.
13 is a fragmentary cross sectional elevation view illustrative of a novel lead-on-chip structure of a semiconductor device in a third embodiment in accordance with the present invention.
FIG. 14 is a fragmentary cross sectional elevation view illustrative of a novel lead-on-chip structure semiconductor device packaged with a sealing resin wherein a semiconductor chip had received 3S up-force by a molten resin when the resin was injected into dies in a third embodiment in accordance with the present invention.
0) Page Pf-2090/nec/Australia/mh FIG. 15 is a fragmentary cross sectional elevation view illustrative of a novel lead-on-chip structure semiconductor device packaged with a sealing resin wherein a semiconductor chip had received down-force by a molten resin when the resin was injected into dies in a 6 third embodiment in accordance with the present invention.
FIG. 16 is a fragmentary plane view illustrative of a novel leadon-chip structure of a semiconductor device in a fourth embodiment in accordance with the present invention.
FIG. 17 is a fragmentary plane view illustrative of a novel lead- 1o on-chip structure of a semiconductor device in a fifth embodiment in accordance with the present invention.
FIG. 18 is a fragmentary cross sectional elevation view illustrative of a novel lead-on-chip structure of a semiconductor device in a fifth embodiment in accordance with the present invention.
is- FIG. 19 is a fragmentary cross sectional elevation view illustrative of a novel lead-on-chip structure semiconductor device packaged with a sealing resin wherein a semiconductor chip had received up-force by a molten resin when the resin was injected into dies in a fifth embodiment in accordance with the present invention.
2-o FIG. 20 is a fragmentary cross sectional elevation view illustrative of a novel lead-on-chip structure semiconductor device packaged with a sealing resin wherein a semiconductor chip had received down-force by a molten resin when the resin was injected into dies in a fifth embodiment in accordance with the present invention.
2 on2-ci FIG. 21 is a fragmentary plane view illustrative of a novel leadon-chip structure of a semiconductor device in a sixth embodiment in accordance with the present invention.
FIG. 22 is a fragmentary plane view illustrative of a novel leadon-chip structure of a semiconductor device in a seventh embodiment in accordance with the present invention.
FIG. 23 is a fragmentary cross sectional elevation view illustrative of a novel lead-on-chip structure of a semiconductor device in a seventh embodiment in accordance with the present invention.
FIG. 24 is a fragmentary cross sectional elevation view 3- illustrative of a novel lead-on-chip structure semiconductor device packaged with a sealing resin wherein a semiconductor chip had received Page 16 Pf-2090/nec/Australia/mh up.-force by a molten resin when the resin was injected into dies in a seventh embodiment in accordance with the present invention.
FIG. 25 is a fragmentary cross sectional elevation view illustrative of a novel lead-on-chip structure semiconductor device packaged with a sealing resin wherein a semiconductor chip had received down-force by a molten resin when the resin was injected into dies in a seventh embodiment in accordance with the present invention.
FIG. 26 is a fragmentary plane view illustrative of a novel leadon-chip structure of a semiconductor device in an eighth embodiment in C) accordance with the present invention.
TIG. 27 is a fragmentary plane view on-chip structure of a semiconductor device accordance with the present invention.
TIG. 28 is a fragmentary plane view Is- on-chip structure of a semiconductor device accordance with the present invention.
FIG. 29 is a fragmentary plane view on;-chip structure of a semiconductor device in accordance with the present invention.
2 o FIG. 30 is a fragmentarv cross illustrative of a novel leadin a ninth embodiment in illustrative of a novel leadin a tenth embodiment in illustrative of a novel leadan eleventh embodiment in sectional elevation view illustrative of a novel lead-on-chip structure of a semiconductor device in an eleventh embodiment in accordance with the present invention.
FIG. 31 is a fragmentary cross sectional elevation view illustrative of a novel lead-on-chip structure semiconductor device ,2,s7 packaged with a sealing resin wherein a semiconductor chip had received up-force by a molten resin when the resin was injected into dies in an eleventh embodiment in accordance with the present invention.
I FIG. 32 is a fragmentary cross sectional elevation view illustrative of a novel lead-on-chip structure semiconductor device 3o packaged with a sealing resin wherein a semiconductor chip had received down-force by a molten resin when the resin was injected into dies in an eleventh embodiment in accordance with the present invention.
FIG. 33 is a fragmentary cross sectional elevation view illustrative of a novel chip-on-lead structure of a semiconductor d6ice in a twelfth embodiment in accordance with the present invention.
(0 Page 17 DETAILED DESCRIPTION The first broad aspect of the present invention provides an adhering structure between a semiconductor chip and two alignments Of first side inner leads and second side inner leads extending in first and second sides of the 57 semiconductor chip respectively. Each of the first and second side inner leads has a stitched portion. The first and second sides are separated by a center line of the semiconductor chip. The semiconductor chip and the first and second side inner leads are adhered to each other by first and second side electrically insulative adhesive tapes respectively. Each of the first and o second side electrically insulative adhesive tapes has both surfaces with adhesion force. The first and second side electrically ins ulative adhesive tapes extend on first and second inner stripe regions so as to adhere the stitched portions of the first and secon~d side inner leads respectively. It is also important that each of the first and second side electrically insulative ty.*I adhesive tapes is further present in at least two positions which are spaced b...from each other in a direction parallel to the center line and which are also *located in the vicinity of an edge of the semiconductor chip, where the edge *::.extends substantially in parallel to the center line, so that the inner leads, .which extend through the two positions, are also fixed in the vicinity of the 2- c edge of the semiconductor chip.
In accordance with a broad aspect of the present invention, the semiconductor chip adthe ine ed aligned are fxdby teelectrically nuaiedhsv tape at a plurality of positions which are distanced from each other -to keep a positional balance of fixing points so as to certainly prevent the any 2S substantive movement of the semiconductor chip particularly in the direction vertical to the surface of the semiconductor chip. Namely, the presence of the electrically insulative adhesive tape at least the two positions spaced from each other in the direction parallel to the center line and which are also located in the vicinity of the edge of the semiconductor 3o chip would result in that inner leads, which extend through the two positions, are fixed not only at the stitched portion but also outside portion in the vicinity of the edge of the semiconductor chip. This structure is capable of certainly preventing a .substantive movement of the semiconductor chip in a direction vertical to the surface of the semiconductor chip by pressure of the flow of the molten resin when the Page 18 Pf-2090/nec/Australia/mh resin is injected into dies for packaging the semiconductor chip. The certain prevention of the substantive movement of the semiconductor chip would result in a certain prevention of the inner leads from being made into contact with the edge of the semiconductor chip. The certain prevention of 6 the substantive movement of the semiconductor chip would also result in a certain prevention of the top portion of the semiconductor device such as tops of bonding wires from exposure from the sealing resin. The certain prevention of the substantive movement of the semiconductor chip would also result in a certain prevention of the bottom portion of the to semiconductor device such as bottom surface of the semiconductor chip or the inner leads from exposure from the sealing resin. The certain prevention of the substantive movement of the semiconductor chip means that the above structure is also capable of keeping a constant distance between the semiconductor chip and the inner lead extending over the Ssemiconductor chip. The certain prevention of the substantive movement of the semiconductor chip also means that the structure is capable of keeping a balance in thickness between upper and lower portions of the sealing resin packaging the semiconductor chip due to no substantive movement 0nor shift in the direction vertical to the surface of the semiconductor chip.
2o Keeping the balance in thickness between upper and lower portions of the sealing resin prevents formation of any thickness-reduced portion, resulting a remarkable reduction in the probability in appearance of crack on the thickness-reduced portion of the resin. From the above description, it can be. understood that the above novel structure allows a high yield of 2s- manufacturing the semiconductor device and also allows the semiconductor device to have a high reliability.
In practice, it is preferable that each of the first and second side electrically insulative adhesive tapes is further positioned so as to adhere outer-most two of the inner leads.
It is further preferable that the outer-most two of the inner leads have spread portions which are adhered with the electrically insulative adhesive tape, so as to increase an adhering area between the inner leads and the electrically insulative adhesive tape and decrease a contact area between the electrically insulative adhesive tape with a sealing resin 36 material for packaging the semiconductor chip. If an adhesion force of the electrically insulative adhesive tape with the sealing resin is relatively weak, Page 19 Pf-2090/nec/Australia/mh it is particularly effective to reduce the contact area between the electrically insulative adhesive tape and the sealing resin for obtaining a high fixing force between the semiconductor chip and the sealing resin.
It is also preferable that each of the first and second side s electrically insulative adhesive tapes is further positioned so as to adhere secondly outer two of the inner leads.
It is further preferable that the secondly outer two of the inner leads have spread portions which are adhered with the electrically insulative adhesive tape, so as to increase an adhering area between the inner leads and the electrically insulative adhesive tape and decrease a contact area between the electrically insulative adhesive tape with a sealing resin material for packaging the semiconductor chip. If an adhesion force of the electrically insulative adhesive tape with the sealing resin is relatively weak, it is particularly effective to reduce the contact area between the electrically insulative adhesive tape and the sealing resin for obtaining a high fixing force between the semiconductor chip and the sealing resin.
It is also preferable that each of the first and second side electrically insulative adhesive tapes is further positioned so as to adhere 2 o outer-most two and secondly outer two of the inner leads.
It is further preferable that the outer-most two and the secondly outer two of the inner leads have spread portions which are adhered with the electrically insulative adhesive tape, so as to increase an adhering area between the inner leads and the electrically insulative adhesive tape and decrease a contact area between the electrically insulative adhesive tape with a sealing resin material for packaging the semiconductor chip. If an adhesion force of the electrically insulative adhesive tape with the sealing resin is relatively weak, it is particularly effective to reduce the contact area .'-'.between the electrically insulative adhesive tape and the sealing resin for 3o obtaining a high fixing force between the semiconductor chip and the sealing resin.
It is also preferable that each of the first and second side electrically insulative adhesive tapes is further positioned so as to adhere outer-most one of the inner leads and secondly outer one in an opposite 3sside to the outer-most one.
It is further preferable that the outer-most one of the inner leads Page Pf-2090/nec/Australia/mh and the secondly outer one in an opposite side to the outer-most one of the inner leads have spread portions which are adhered with the electrically insulative adhesive tape, so as to increase an adhering area between the inner leads and the electrically insulative adhesive tape and decrease a s contact area between the electrically insulative adhesive tape with a sealing resin material for packaging the semiconductor chip. If an adhesion force of the electrically insulative adhesive tape with the sealing resin is relatively weak, it is particularly effective to reduce the contact area between the electrically insulative adhesive tape and the sealing resin for io obtaining a high fixing force between the semiconductor chip and the sealing resin.
It is also preferable that each of the first and second side electrically insulative adhesive tapes further extends on an outer stripe region in the vicinity of and in parallel to the edge of the semiconductor chip, where the outer stripe region is separated from the inner stripe region, t and an outside edge of the each of the first and second side electrically insulative adhesive tapes is positioned inside of the edge of the semiconductor chip.
It is further preferable that the inner leads have spread portions 2 c which are adhered with the electrically insulative adhesive tape, provided that the spread portions of the adjacent two of the inner leads are separated from each other, so as to increase an adhering area between the inner leads and the electrically insulative adhesive tape and decrease a contact area between the electrically insulative adhesive tape with a sealing resin 2S' material for packaging the semiconductor chip. If an adhesion force of the electrically insulative adhesive tape with the sealing resin is relatively weak, it is particularly effective to reduce the contact area between the electrically :insulative adhesive tape and the sealing resin for obtaining a high fixing force between the semiconductor chip and the sealing resin.
3 It is also preferable that each of the first and second side electrically insulative adhesive tapes further extends on an outer stripe region along the edge of the semiconductor chip, where the outer stripe region is separated from the inner stripe region, and an outside edge of the each of the first and second side electrically insulative adhesive tapes is positioned in correspondence to the edge of the semiconductor chip.
It is further preferable that the inner leads have spread portions Page 21 which are adhered with the electrically insulative adhesive tape, provided that the spread portions of the adjacent two of the inner leads are separated from each other, so as to increase an adhering area between the inner leads and the electrically insulative adhesive tape and decrease a contact area between the electrically insulative adhesive tape with a sealing resin material for packaging the semiconductor chip. If an adhesion force of the electrically insulative adhesive tape with the sealing resin is relatively weak, it is particularly effective to reduce the contact area between the electrically insulative adhesive tape and the sealing resin for obtaining a high fixng 'o force between the semiconductor chip and the sealing resin.
It is also preferable that each of the first and second side electrically insulative adhesive tapes continuously extends from the inner stripe region to the outer stripe region in the vicinity of and in parallel to the edge of the semiconductor chip so-that an outside edge of the each of the first and second side electrically insulative adhesive tapes is positioned inside of the edge of the semiconductor chip. If an adhesion force of the electrically insulative adhesive tape with the sealing resin is sufficiently strong, there is raised no problem with increase in contact area between the electrically insulative adhesive tape and the sealing resin.
2o It is also preferable that each of the first and second side electrically insulative adhesive tapes continuously extends from the inner stripe region through the edge of the semiconductor chip so that an outside edge of the each of the first and second side electrically insulative adhesive tapes is positioned in correspondence to the edge of the semiconductor chip.
2 If an adhesion force of the electrically insulative adhesive tape with the sealing resin is sufficiently strong, there is raised no problem with increase in contact area between the electrically insulative adhesive tape and the sealing resin.
The second broad aspect of the present invention provides an electrically insulative o adhesive tape structure to be used for adhering a semiconductor chip with inner leads. The inner leads extend substantially in parallel to each other.
The inner leads are aligned in a direction substantially in parallel to an edge of the semiconductor chip. Each of the inner leads has an inside portion.
The semiconductor chip and the inner leads are adhered to each other by the electrically insulative adhesive tape. The electrically insulative adhesive tape has both surfaces with adhesion force. The electrically insulative Page 22 adhesive tape extends on an inner stripe region so as to adhere the inside portions of the inner leads. It is also important that the electrically insulative adhesive tape is further present in at least two Positions which are. spaced from each other in a direction parallel to the edge of the 6- semiconductor chip and which are also located in the vicinity of -the edge of the semiconductor chip so that the inner leads, which extend through the two positions, are also adhered in the vicinity of the edge of the semiconductor chip.
In accordance with a broad aspect of the present invention, the semiconductor chip /o and the inner leads aligned are fixed by the electrically insulative adhesive tape at a plurality of positions which are distanced from each other to keep a positional balance of fixing points so as to certainly prevent the any substantive movement of the semiconductor chip particularly in the direction vertical to the surface of-the semiconductor chip. Namely, the IS7 presence of the electrically insulative adhesive tape at least the two positions spaced from each other in the direction parallel to the center line and which are also located in the vicinity of the edge of the semiconductor chip would result in that inner leads, which extend through the two positions, aefixed not only at the stitched portion but also outside portion in the vicinity of the edge of the semiconductor chip. T'his structure is capable of certainly preventing a substantive movement of the semiconductor chip in a direction vertical to the surface of the semiconductor chip by pressure of the flow of the molten resin when the resin is injected into dies for packaging the semiconductor chip. The certain 2s-prevention of the substantive movement of the semiconductor chip would result in a certain prevention of the inner leads from being made into 4% contact with the edge of the semiconductor chip. The certain prevention of the substantive movement of the semiconductor chip would also result in a certain prevention of the top portion of the semiconductor device such as S O tops of bonding wires from exposure from the sealing resin. The certain prevention of the substantive movement of the semiconductor chip would also result in a certain prevention of the bottom portion of the semiconductor device such as bottom surface of the semiconductor chip or the inner leads from exposure from the sealing resin. The certain prevention of the substantive movement of the semiconductor chip means that the above structure is also capable of keeping a constant distance Page 23 Pf-2090/nec/Australia/mh between the semiconductor chip and the inner lead extending over the semiconductor chip. The certain prevention of the substantive movement of the semiconductor chip also means that the structure is capable of keeping a balance in thickness between upper and lower portions of the sealing s resin packaging the semiconductor chip due to no substantive movement nor shift in the direction vertical to the surface of the semiconductor chip.
Keeping the balance in thickness between upper and lower portions of the sealing resin prevents formation of any thickness-reduced portion, resulting in a remarkable reduction in the probability in appearance of crack on the io thickness-reduced portion of the resin. From the above description, it can be understood that the above novel structure allows a high yield of manufacturing the semiconductor device and also allows the semiconductor device to have a high reliability.
It is preferable that the electrically insulative adhesive tape is i& further positioned so as to adhere outer-most two of the inner leads.
It is further preferable that the outer-most two of the inner leads have spread portions which are adhered with the electrically insulative adhesive tape, so as to increase an adhering area between the inner leads and the electrically insulative adhesive tape and decrease a contact area between the electrically insulative adhesive tape with a sealing resin material for packaging the semiconductor chip. If an adhesion force of the electrically insulative adhesive tape with the sealing resin is relatively weak, it is particularly effective to reduce the contact area between the electrically insulative adhesive tape and the sealing resin for obtaining a high fixing 2- force between the semiconductor chip and the sealing resin.
It is also preferable that the electrically insulative adhesive tape is further positioned so as to adhere secondly outer two of the inner leads.
It is further preferable that the secondly outer two of the inner leads have spread portions which are adhered with the electrically so insulative adhesive tape, so as to increase an adhering area between the inner leads and the electrically insulative adhesive tape and decrease a contact area between the electrically insulative adhesive tape with a sealing resin material for packaging the semiconductor chip. If an adhesion force of the electrically insulative adhesive tape with the sealing resin is 3S-" relatively weak, it is particularly effective to reduce the contact area between the electrically insulative adhesive tape and the sealing resin for Q Page 24 Pf-2090/nec/Australia/mh obtaining a high fixing force between the semiconductor chip and the sealing resin.
It is also preferable that the electrically insulative adhesive tape is further positioned so as to adhere outer-most two and secondly outer two of the inner leads.
It is further preferable that the outer-most two and the secondly outer two of the inner leads have spread portions which are adhered with the electrically insulative adhesive tape, so as to increase an adhering area between the inner leads and the electrically insulative adhesive tape and to decrease a contact area between the electrically insulative adhesive tape with a sealing resin material for packaging the semiconductor chip. If an adhesion force of the electrically insulative adhesive tape with the sealing resin is relatively weak, it is particularly effective to reduce the contact area between the electrically insulative adhesive tape and the sealing resin for Is obtaining a high fixing force between the semiconductor chip and the sealing resin.
It is also preferable that the electrically insulative adhesive tape is further positioned so as to adhere outer-most one of the inner leads and secondly outer one in an opposite side to the outer-most one.
0 It is further preferable that the outer-most one of the inner leads and the secondly outer one in an opposite side to the outer-most one of the inner leads have spread portions which are adhered with the electrically insulative adhesive tape, so as to increase an adhering area between the inner leads and the electrically insulative adhesive tape and decrease a 25 contact area between the electrically insulative adhesive tape with a sealing resin material for packaging the semiconductor chip. If an adhesion force of the electrically insulative adhesive tape with the sealing resin is .relatively weak, it is particularly effective to reduce the contact area between the electrically insulative adhesive tape and the sealing resin for obtaining a high fixing force between the semiconductor chip and the sealing resin.
It is also preferable that the electrically insulative adhesive tapes further extend on an outer stripe region in the vicinity of and in parallel to the edge of the semiconductor chip, where the outer stripe region is 3 separated from the inner stripe region, and an outside edge of the electrically insulative adhesive tape is positioned inside of the edge of the ~Page p iP Pf-2090/nec/Australia/mh semiconductor chip.
It is further preferable that the inner leads have spread portions which are adhered with the electrically insulative adhesive tape, provided that the spread portions of the adjacent two of the inner leads are separated from each other, so as to increase an adhering area between the inner leads and the electrically insulative adhesive tape and decrease a contact area between the electrically insulative adhesive tape with a sealing resin material for packaging the semiconductor chip. If an adhesion force of the electrically insulative adhesive tape with the sealing resin is relatively weak, o it is particularly effective to reduce the contact area between the electrically insulative adhesive tape and the sealing resin for obtaining a high fixing force between the semiconductor chip and the sealing resin.
It is also preferable that the electrically insulative adhesive tape further extends on an outer stripe region along the edge of the is semiconductor chip, where the outer stripe region is separated from the inner stripe region, and an outside edge of the electrically insulative adhesive tape is positioned in correspondence to the edge of the semiconductor chip.
It is further preferable that the inner leads have spread portions 20 which are adhered with the electrically insulative adhesive tape, provided that the spread portions of the adjacent two of the inner leads are separated from each other, so as to increase an adhering area between the inner leads and the electrically insulative adhesive tape and decrease a contact area between the electrically insulative adhesive tape with a sealing resin 25: material for packaging the semiconductor chip. If an adhesion force of the electrically insulative adhesive tape with the sealing resin is relatively weak, it is particularly effective to reduce the contact area between the electrically .i insulative adhesive tape and the sealing resin for obtaining a high fixing force between the semiconductor chip and the sealing resin.
3o It is also preferable that the electrically insulative adhesive tape continuously extends from the inner stripe region to the outer stripe region in the vicinity of and in parallel to the edge of the semiconductor chip so that an outside edge of the electrically insulative adhesive tape is positioned inside of the edge of the semiconductor chip. If an adhesion force of the electrically insulative adhesive tape with the sealing resin is sufficiently strong, there is raised no problem with increase in contact area between the Page 26 electrically insulative adhesive tape and the sealing resin.
It is also preferable that the electrically insulative adhesive tape continuously extends from the inner stripe region through the edge of the semiconductor chip so that an outside edge of the electrically insulative adhesive tape is positioned in correspondence to the edge of the semiconductor chip. If an adhesion force of the electrically insulative adhesive tape with the sealing resin is sufficiently strong, there is raised no problem with increase in contact area between the electrically insulative adhesive tape and the sealing resin.
o0 The third broad aspect of the present invention provides a lead-on-chip structure of a semiconductor device packaged with a sealing resin. The lead-on-chip structure comprises the following elements. A semiconductor chip has a top surface which further has two alignments of bonding pads along opposite sides of a center line of the semiconductor chip. The center line separates s- the semiconductor chip into first and second side regions. First and second alignments of inner leads extend over the first and second side regions of the semiconductor chip respectively so that the inner leads are spaced from the 'top surface of the semiconductor chip. The inner leads have stitched portions positioned in inside terminal portions thereof. The stitched 20 portions of the inner leads are positioned outside of the bonding pads. The inner leads extend substantially in parallel to each other and along a direction vertical to the center line of the semiconductor chip. Bonding wires electrically connect the stitched portions of the inner leads to corresponding ones of the bonding pads of the semiconductor chip. First 2s- and second side electrically insulative adhesive tapes have top and bottom Surfaces with adhesion force. The bottom surfaces of the first and second side electrically insulative adhesive tapes are adhered on first and second inner stripe regions of the semiconductor chip. The first and second inner stripe regions are positioned outside of the bonding pads, and also the top surfaces of the first and second side electrically insulative adhesive tapes are adhered on bottom surfaces of the stitched portions of the inner leads, so, as to provide adhesions between the stitched portions of the inner leads and the first and second inner stripe regions of the semiconductor chip. It is also important that each of the first and second side electrically insulative o adhesive tapes is further present in at least two positions which are spaced from each other in a direction parallel to the center line and which are also Page 27 located in the vicinity of an edge of the semiconductor chip, where the edge extends substantially in parallel to the center line, so that the inner leads, which extend through the two positions, are also fixed in the vciiyo h edge of the semiconductor chip.vintyote In accordance with a broad aspect of the present invention, the semiconductor chip and the inner leads aligned are fixed by the electrically insulative adhesive tape at a plurality of positions which are distanced from each other to keep a positional balance of fixing points so as to- certainly prevent the any substantive movement of the semiconductor chip particularly in the o0 direction vertical to the surface of the semiconductor chip. Namely, the presence of the electrically insulative adhesive tape at least the two positions spaced from each other in the direction parallel to the center line and which are also located in the vicinity of the edge of the semiconductor chip would result in that inner leads, which extend through the two t 5 positions, are fixed not only at the stitched portion but also outside portion in the vicinity of the edge of the semiconductor chip. This structure is capable of certainly preventing a substantive movement of the semiconductor chip in a direction vertical to the surface of the semiconductor chip by pressure of the flow of the molten resin when the 2)resin is injected into dies for packaging the semiconductor chip. The certain prevention of the substantive movement of the semiconductor chip would result in a certain prevention of the inner leads from being made into contact with the edge of the semiconductor chip. The certain prevention of the -substantive movement of the semiconductor chip would also result in a certain prevention of the top portion of the semiconductor device such as tops of bonding wires from exposure from the sealing resin. The certain prevention of the substantive movement of the semiconductor chip would also result in a certain prevention of the bottom portion of the semiconductor device such as bottom surface of the semiconductor chip from exposure from the sealing resin. The certain prevention of the substantive movement of the semiconductor chip means that the above structure is also capable of keeping a constant distance between the semiconductor chip and the inner lead extending over the semiconductor chip. The certain prevention of the substantive movement of the &'semiconductor chip also means that the structure is capable of keeping a balance in thickness between upper and lower portions of the sealing resin Page 28 Pf-2090/nec/Australia/mh packaging the semiconductor chip due to no substantive movement nor shift in the direction vertical to the surface of the semiconductor chip.
Keeping the balance in thickness between upper and lower portions of the sealing resin prevents formation of any thickness-reduced portion, resulting 6- in aremarkable reduction in the probability in appearance of crack on the thickness-reduced portion of the resin. From the above description, it can be understood that the above novel structure allows a high yield of manufacturing the semiconductor device and also allows the semiconductor device to have a high reliability.
to It is preferable that each of the first and second side electrically insulative adhesive tapes is further positioned so as to adhere outer-most two of the inner leads.
It is further preferable that the outer-most two of the inner leads have spread portions which are adhered with the electrically insulative adhesive tape, so as to increase an adhering area between the inner leads and the electrically insulative adhesive tape and decrease a contact area between the electrically insulative adhesive tape with a sealing resin material for packaging the semiconductor chip. If an adhesion force of the :.°..electrically insulative adhesive tape with the sealing resin is relatively weak, o it is particularly effective to reduce the contact area between the electrically insulative adhesive tape and the sealing resin for obtaining a high fixing force between the semiconductor chip and the sealing resin.
It is also preferable that each of the first and second side electrically insulative adhesive tapes is further positioned so as to adhere 2s secondly outer two of the inner leads.
It is further preferable that the secondly outer two of the inner leads have spread portions which are adhered with the electrically insulative adhesive tape, so as to increase an adhering area between the ::inner leads and the electrically insulative adhesive tape and decrease a
S
contact area between the electrically insulative adhesive tape with a sealing resin material for packaging the semiconductor chip. If an adhesion force of the electrically insulative adhesive tape with the sealing resin is relatively weak, it is particularly effective to reduce the contact area between the electrically insulative adhesive tape and the sealing resin for 3S- obtaining a high fixing force between the semiconductor chip and the sealing resin.
0 Page 29 Pf-2090/nec/Australia/mh It is, also preferable that each of the first and second side electrically insulative adhesive tapes is further positioned so as to adhere outer-most two and secondly outer two of the inner leads.
It is further preferable that the outer-most two and the secondly outer two of the inner leads have spread portions which are adhered with the, electrically insulative adhesive tape, so as to increase an adhering area between the inner leads and the electrically insulative adhesive tape and decrease a contact area between the electrically insulative adhesive tape with a sealing resin material for packaging the semiconductor chip. If an io adhesion force of the electrically insulative adhesive tape with the sealing resin is relatively weak, it is particularly effective to reduce the contact area between the electrically insulative adhesive tape and the sealing resin for obtaining a high fixing force between the semiconductor chip and the sealing resin.
is also preferable that each of the first and second side electrically insulative adhesive tapes is further positioned so as to adhere outer-most one of the inner leads and secondly outer one in an opposite side to the outer-most one.
It is further preferable that the outer-most one of the inner leads 2,0 and the secondly outer one in an opposite side to the outer-most one of the inner leads have spread portions which are adhered with the electrically insulative adhesive tape, so as to increase an adhering area between the inner leads and the electrically insulative adhesive tape and decrease a contact area between the electrically insulative adhesive tape with a sealing 2- resin material for packaging the semiconductor chip. If an adhesion force of the electrically insulative adhesive tape with the sealing resin is relatively weak, it is particularly effective to reduce the contact area between the electrically insulative adhesive tape and the sealing resin for obtaining a high fixing force between the semiconductor chip and the 0 sealing resin.
It is also preferable that each of the first and second side electrically insulative adhesive tapes further extends on an outer stripe region in the vicinity of and in parallel to the edge of the semiconductor chip, where the outer stripe region is separated from the inner stripe region, 3" and an outside edge of the each of the first and second side electrically insulative adhesive tapes is positioned inside of the edge of the C0) Page Pf-2090/nec/Australia/mh semiconductor chip.
It is further preferable that the inner leads have spread portions which are adhered with the electrically insulative adhesive tape, provided that the spread portions of the adjacent two of the inner leads are separated from each other, so as to increase an adhering area between the inner leads and the electrically insulative adhesive tape and decrease a contact area between the electrically insulative adhesive tape with a sealing resin material for packaging the semiconductor chip. If an adhesion force of the electrically insulative adhesive tape with the sealing resin is relatively weak, 1o it is particularly effective to reduce the contact area between the electrically insulative adhesive tape and the sealing resin for obtaining a high fixing force between the semiconductor chip and the sealing resin.
It is also preferable that each of the first and second side electrically insulative adhesive tapes further extends on an outer stripe is- region along the edge of the semiconductor chip, where the outer stripe region is separated from the inner stripe region, and an outside edge of the each of the first and second side electrically insulative adhesive tapes is positioned in correspondence to the edge of the semiconductor chip.
It is further preferable that the inner leads have spread portions 20 which are adhered with the electrically insulative adhesive tape, provided that the spread portions of the adjacent two of the inner leads are separated from each other, so as to increase an adhering area between the inner leads and the electrically insulative adhesive tape and decrease a contact area between the electrically insulative adhesive tape with a sealing resin 2s" material for packaging the semiconductor chip. If an adhesion force of the S.electrically insulative adhesive tape with the sealing resin is relatively weak, it is particularly effective to reduce the contact area between the electrically insulative adhesive tape and the sealing resin for obtaining a high fixing force between the semiconductor chip and the sealing resin.
o It is also preferable that each of the first and second side electrically insulative adhesive tapes continuously extends from the inner stripe region to the outer stripe region in the vicinity of and in parallel to the edge of the semiconductor chip so that an outside edge of the each of the first and second side electrically insulative adhesive tapes is positioned 3s inside of the edge of the semiconductor chip. If an adhesion force of the electrically insulative adhesive tape with the sealing resin is sufficiently Page 31 §trong, there is raised no problem with increase in contact area between the electrically insulative adhesive tape and the sealing resin.
It is also preferable that each of the first and second side electrically insulative adhesive tapes continuously extends from the inner stripe region through the edge of the semiconductor chip so that an outside edge of the each of the first and second side electrically insulative adhesive tapes is positioned in correspondence to the edge of the semiconductor chip.
If an adhesion force of the electrically insulative adhesive tape with the sealing resin is sufficiently strong, there is raised no problem with increase i in contact area between the electrically insulative adhesive tape and the sealing resin.
The fourth broad aspect of the present invention provides a chip-on-lead structure of a semiconductor device packaged with a sealing resin. The chip-on-lead structure comprises the following elements. A semiconductor chip has a top surface which further has two alignments of bnding pads along opposite sides of the semiconductor chip. The center line separates the semiconductor chip into first and second side regions. First and second alignments of inner leads extend under the first and second side regions of a bottom surface of the semiconductor chip. The inner leads have stitched portions positioned in inside terninal portions thereof. The inner leads extend substantially in parallel to each other and along a direction vertical to the center line of the semiconductor chip. Bonding wires electrically connect the inner leads to corresponding ones of the bonding pads of the 2 semiconductor chip. First and second side electrically insulative adhesive tapes have top and bottom surfaces with adhesion force. The top surfaces of the first and second side electrically insulative adhesive tapes are adhered on first and second inner stripe regions of the semiconductor chip, and also "i the .bottom surfaces of the first and second side electrically insulative 3o adhesive tapes are adhered on top surfaces of the stitched portions of the inner leads, so as to provide adhesions between the stitched portions of the inner leads and the first and second inner stripe regions of the semiconductor chip. It is also important that each of the first and second side electrically insulative adhesive tapes is further present in at least two positions which are spaced from each other in a direction parallel to the center line and which are also located in the vicinity of an edge of the Page 32 semiconductor chip, where the edge extends substantially in paralle I to the center line, so that the inner leads, which extend through the two positions, are also fixed in the vicinity of the edge of the semiconductor chip.
in accordance with a broad aspect of the present invention, the semiconductor chip and the inner leads aligned are fixed by the electrically insulative adhesive tape at a plurality of positions which are distanced from each other to keep a positional balance of fixing points so as to certainly prevent the any Substantive movement of the semiconductor chip particularly in the direction vertical to the surface of the semiconductor chip. Namely, the presence of the electrically insulative adhesive tape at least the two positions spaced from each other in the direction parallel to the center line and which are also located in the vicinity of the edge of the semiconductor chip would result in that inner leads, which extend through the two positions, are fixed not only at the stitched portion but also outside portion 16 in the vicinity of the edge of the semiconductor chip. This structure is capable of certainly preventing a substantive movement of the semiconductor chip in a direction vertical to the surface of the semniconductor chip by pressure of the flow of the molten resin when the resin is injected into dies for packaging the semiconductor chip. The certain prevention of the substantive movement of the semiconductor chip would result in a certain prevention of thc inner leads from being made into contact with the edge of the semiconductor chip. The certain prevention of the substantive movement of the semiconductor chip would also result in a certain prevention of the top portion of the semiconductor device such as tops of bonding wires from exposure from the sealing resin. The certain prevention ofthe substantive movement of the semiconductor chip would also result in a certain prevention of the bottom portion of the semiconductor device such as bottom surface of the inner leads from '0000 exposure from the sealing resin. The certain prevention of the substantive 0003 movement of the semiconductor chip means that the above structure is also capable of keeping a constant distance between the semiconductor chip and the inner lead extending over the semiconductor chip. The certain prevention of the substantive movement of the semiconductor chip also means that the structure is capable of .keeping a balance in thickness 3S-- between upper and lower portions of the sealing resin packaging the semiconductor chip due to no substantive movement nor shift in the Page 33 Pf-2090/nec/Australia/mh direction vertical to the surface of the semiconductor chip. Keeping the balance in thickness between upper and lower portions of the sealing resin prevents formation of any thickness-reduced portion, resulting in a remarkable reduction in the probability in appearance of crack on the s- thickness-reduced portion of the resin. From the above description, it can be understood that the above novel structure allows a high yield of manufacturing the semiconductor device and also allows the semiconductor device to have a high reliability.
It is preferable that each of the first and second side electrically 1o insulative adhesive tapes is further positioned so as to adhere outer-most two of the inner leads.
It is further preferable that the outer-most two of the inner leads have spread portions which are adhered with the electrically insulative adhesive tape, so as to increase an adhering area between the inner leads Is and the electrically insulative adhesive tape and decrease a contact area between the electrically insulative adhesive tape with a sealing resin material for packaging the semiconductor chip. If an adhesion force of the *000 :....electrically insulative adhesive tape with the sealing resin is relatively weak, it is particularly effective to reduce the contact area between the electrically 20 insulative adhesive tape and the sealing resin for obtaining a high fixing force between the semiconductor chip and the sealing resin.
It is also preferable that each of the first and second side electrically insulative adhesive tapes is further positioned so as to adhere secondly outer two of the inner leads.
2S- It is further preferable that the secondly outer two of the inner leads have spread portions which are adhered with the electrically insulative adhesive tape, so as to increase an adhering area between the .i inner leads and the electrically insulative adhesive tape and decrease a contact area between the electrically insulative adhesive tape with a sealing 2o resin material for packaging the semiconductor chip. If an adhesion force of the electrically insulative adhesive tape with the sealing resin is relatively weak, it is particularly effective to reduce the contact area between the electrically insulative adhesive tape and the sealing resin for obtaining a high fixing force between the semiconductor chip and the sealing resin.
It is also preferable that each of the first and second side Page 34 Pf-2090/nec/Australia/mh electrically insulative adhesive tapes is further positioned so as to adhere outer-most two and secondly outer two of the inner leads.
It is further preferable that the outer-most two and the secondly outer two of the inner leads have spread portions which are adhered with 6 the electrically insulative adhesive tape, so as to increase an adhering area between the inner leads and the electrically insulative adhesive tape and decrease a contact area between the electrically insulative adhesive tape with a sealing resin material for packaging the semiconductor chip. If an adhesion force of the electrically insulative adhesive tape with the sealing to resin is relatively weak, it is particularly effective to reduce the contact area between the electrically insulative adhesive tape and the sealing resin for obtaining a high fixing force between the semiconductor chip and the sealing resin.
It is also preferable that each of the first and second side Is electrically insulative adhesive tapes is further positioned so as to adhere outer-most one of the inner leads and secondly outer one in an opposite side to the outer-most one.
It is further preferable that the outer-most one of the inner leads and the secondly outer one in an opposite side to the outer-most one of the 2o inner leads have spread portions which are adhered with the electrically insulative adhesive tape, so as to increase an adhering area between the inner leads and the electrically insulative adhesive tape and decrease a contact area between the electrically insulative adhesive tape with a sealing resin material for packaging the semiconductor chip. If an adhesion force 2s of the electrically insulative adhesive tape with the sealing resin is relatively weak, it is particularly effective to reduce the contact area between the electrically insulative adhesive tape and the sealing resin for obtaining a high fixing force between the semiconductor chip and the sealing resin.
0 It is also preferable that each of the first and second side electrically insulative adhesive tapes further extends on an outer stripe region in the vicinity of and in parallel to the edge of the semiconductor chip, where the outer stripe region is separated from the inner stripe region, and an outside edge of the each of the first and second side electrically Sinsulative adhesive tapes is positioned inside of the edge of the semiconductor chip.
0 Page Pf-2090/nec/Australia/mh It is further preferable that the inner leads have spread portions which are adhered with the electrically insulative adhesive tape, provided that the spread portions of the adjacent two of the inner leads are separated from each other, so as to increase an adhering area between the inner leads 56 and the electrically insulative adhesive tape and decrease a contact area between the electrically insulative adhesive tape with a sealing resin material for packaging the semiconductor chip. If an adhesion force of the electrically insulative adhesive tape with the sealing resin is relatively weak, it is particularly effective to reduce the contact area between the electrically o insulative adhesive tape and the sealing resin for obtaining a high fixing force between the semiconductor chip and the sealing resin.
It is also preferable that each of the first and second side electrically insulative adhesive tapes further extends on an outer stripe region along the edge of the semiconductor chip, where the outer stripe )E region is separated from the inner stripe region, and an outside edge of the each of the first and second side electrically insulative adhesive tapes is positioned in correspondence to the edge of the semiconductor chip.
It is further preferable that the inner leads have spread portions which are adhered with the electrically insulative adhesive tape, provided that the spread portions of the adjacent two of the inner leads are separated from each other, so as to increase an adhering area between the inner leads and. the electrically insulative adhesive tape and decrease a contact area between the electrically insulative adhesive tape with a sealing resin material for packaging the semiconductor chip. If an adhesion force of the 2 electrically insulative adhesive tape with the sealing resin is relatively weak, it is particularly effective to reduce the contact area between the electrically 9**o insulative adhesive tape and the sealing resin for obtaining a high fixing force between the semiconductor chip and the sealing resin.
It is also preferable that each of the first and second side 0 &0 electrically insulative adhesive tapes continuously extends from the inner stripe region to the outer stripe region in the vicinity of and in parallel to the- edge of the semiconductor chip so that an outside edge of the each of the first and second side electrically insulative adhesive tapes is positioned inside of the edge of the semiconductor chip. If an adhesion force of the 3S electrically insulative adhesive tape with the sealing resin is sufficiently strong, there is raised no problem with increase in contact area between the Page 36 electrically insulative adhesive tape and the sealing resin.
It -is also preferable that each of the first and second side electrically insulative adhesive tapes continuously extends from the inner stripe region through the edge of the semiconductor chip so that an outside 6 edge of the each of the first and second side electrically insulative adhesive tapes is positioned in correspondence to the edge of the semiconductor chip.
If an adhesion force of the electrically insulative adhesive tape with the sealing resin is sufficiently strong, there is raised no problem with increase in contact area between the electrically insulative adhesive tape and the to sealing resin.
The fifth broad aspect of the present invention provides a lead frame having two alignments of first side inner leads and second side inner leads extending in first and second sides which are separated by a center line along a longitudinal direction of the lead fraine. The first side inner leads have is stitched portions which are adhered with a first side electrically insulative *9 adhesive tape having both surfaces with adhesion force for adhering with a S...semniconductor chip. The second side inner leads also have stitched portions wihare ahrdwith a second side electrically insulative adhesive tape having both surfaces with adhesion force for adhering withth 2o semiconductor chip. It is also important that each of the first and second side electrically insulative adhesive tapes is further present in at least two positions which are spaced from each other in a direction parallel to the center line and which are also located outside of the stitched portions of the 9 inner leads and the two positions are located in the vicinity of chip edge 2,S7 correspondence positions of the inner leads, where the chip edge correspondence position is previously determined to correspond to an edge of the semiconductor chip after the semiconductor chip has been adhered to the lead frame by the first and second electrically insulative adhesive tapes.
In accordance with a broad aspect of the present invention, the above lead frame 3o allows that the semiconductor chip and the inner leads aligned are fixed by the electrically insulative -adhesive tape at a plurality. of positions which are distanced from each other to keep a positional balance of fixing points so as to certainly prevent the any substantive movement of the semiconductor chip particularly in the direction vertical to the surface of the semiconductor chip. Namely, the presence of the electrically irisulative adhesive tape at least the two positions spaced from each other in the Page 37 Pf-2090/nec/Australia/mh direction parallel to the center line and which are also located in the vicinity of the edge of the semiconductor chip would result in that inner leads, which extend through the two positions, are fixed not only at the stitched portion but also outside portion in the vicinity of the edge of the S semiconductor chip. This structure is capable of certainly preventing a substantive movement of the semiconductor chip in a direction vertical to the surface of the semiconductor chip by pressure of the flow of the molten resin when the resin is injected into dies for packaging the semiconductor chip. The certain prevention of the substantive movement of the io semiconductor chip would result in a certain prevention of the inner leads from being made into contact with the edge of the semiconductor chip. The certain prevention of the substantive movement of the semiconductor chip would also result in a certain prevention of the top portion of the semiconductor device such as tops of bonding wires from exposure from i~ the sealing resin. The certain prevention of the substantive movement of the semiconductor chip would also result in a certain prevention of the bottom portion of the semiconductor device such as bottom surface of the semiconductor chip or the inner leads from exposure from the sealing resin.
The certain prevention of the substantive movement of the semiconductor 20 chip means that the above structure is also capable of keeping a constant distance between the semiconductor chip and the inner lead extending over the semiconductor chip. The certain prevention of the substantive movement of the semiconductor chip also means that the structure is capable of keeping a balance in thickness between upper and lower 2s portions of the sealing resin packaging the semiconductor chip due to no substantive movement nor shift in the direction vertical to the surface of the semiconductor chip. Keeping the balance in thickness between upper and *lower portions of the sealing resin prevents formation of any thickness- .mo. reduced portion, resulting in a remarkable reduction in the probability in o appearance of crack on the thickness-reduced portion of the resin. From the above description, it can be understood that the above novel structure allows a high yield of manufacturing the semiconductor device and also allows the semiconductor device to have a high reliability.
It is preferable that each of the first and second side electrically S- insulative adhesive tapes is further positioned so as to adhere outer-most two of the inner leads.
Page 38 Pf-2090/nec/Australia/mh It is further preferable that the outer-most two of the inner leads have spread portions which are adhered with the electrically insulative adhesive tape, so as to increase an adhering area between the inner leads and the electrically insulative adhesive tape and decrease an exposed area of the electrically insulative adhesive tape. If an adhesion force of the electrically insulative adhesive tape with the sealing resin is relatively weak, it is particularly effective to reduce the contact area between the electrically insulative adhesive tape and the sealing resin for obtaining a high fixing force between the semiconductor chip and the sealing resin.
to It is also preferable that each of the first and second side electrically insulative adhesive tapes is further positioned so as to adhere secondly outer two of the inner leads.
It is further preferable that the secondly outer two of the inner leads have spread portions which are adhered with the electrically Is insulative adhesive tape, so as to increase an adhering area between the inner leads and the electrically insulative adhesive tape and decrease an exposed area of the electrically insulative adhesive tape. If an adhesion force of the electrically insulative adhesive tape with the sealing resin is relatively weak, it is particularly effective to reduce the contact area 2- between the electrically insulative adhesive tape and the sealing resin for obtaining a high fixing force between the semiconductor chip and the sealing resin.
It is also preferable that each of the first and second side electrically insulative adhesive tapes is further positioned so as to adhere 2G7 outer-most two and secondly outer two of the inner leads.
.0.00. It is further preferable that the outer-most two and the secondly outer two of the inner leads have spread portions which are adhered with the electrically insulative adhesive tape, so as to increase an adhering area between the inner leads and the electrically insulative adhesive tape and 0Q decrease an exposed area of the electrically insulative adhesive tape. If an adhesion force of the electrically insulative adhesive tape with the sealing resin is relatively weak, it is particularly effective to reduce the contact area between the electrically insulative adhesive tape and the sealing resin for obtaining a high fixing force between the semiconductor chip and the gs- sealing resin.
It is also preferable that each of the first and second side (9 Page 39 Pf-2090/nec/Austraia/mh electrically insulative adhesive tapes is further positioned so as to adhere outer-most one of the inner leads and secondly outer one in an opposite side to the outer-most one.
It is further preferable that the outer-most one of the inner leads and the secondly outer one in an opposite side to the outer-most one of the inner leads have spread portions which are adhered with the electrically insulative adhesive tape, so as to increase an adhering area between the inner leads and the electrically insulative adhesive tape and decrease an exposed area of the electrically insulative adhesive tape. If an adhesion force of the electrically insulative adhesive tape with the sealing resin is relatively weak, it is particularly effective to reduce the contact area between the electrically insulative adhesive tape and the sealing resin for obtaining a high fixing force between the semiconductor chip and the sealing resin.
IS It is also preferable that each of the first and second side electrically insulative adhesive tapes further extends on an outer stripe region over the inner leads in the vicinity of the chip edge correspondence positions, where the outer stripe region is positioned outside of and i separated from the stitched portion, and an outside edge of the each of the zo first and second side electrically insulative adhesive tapes is positioned "..inside of the chip edge correspondence position.
is further preferable that the inner leads have spread portions which are adhered with the electrically insulative adhesive tape, provided that the spread portions of the adjacent two of the inner leads are separated 2s- from'each other, so as to increase an adhering area between the inner leads and the electrically insulative adhesive tape and decrease an exposed area of the electrically insulative adhesive tape. If an adhesion force of the electrically insulative adhesive tape with the sealing resin is relatively weak, it is particularly effective to reduce the contact area between the electrically o insulative adhesive tape and the sealing resin for obtaining a high fixing force between the semiconductor chip and the sealing resin.
It is also preferable that each of the first and second side electrically insulative adhesive tapes further extends on an outer stripe region over the inner leads in the vicinity of the chip edge correspondence positions, where the outer stripe region is positioned outside of and separated from the stitched portion, and an outside edge of the each of the A Page first and second side electrically insulative adhesive tapes is positioned at the chip edge correspondence position.
It is further preferable that the inner leads have spread portions which -are adhered with the electrically insulative adhesive tape, provided s that the spread portions of the adjacent two of the inner leads are separated from each other, so as to increase an adhering area between the inner leads and the electrically insulative adhesive tape and decrease an exposed area of the electrically insulative adhesive tape. If an adhesion force of the electrically insulative adhesive tape with the sealing resin is relatively weak, 'o it is particularly effective to reduce the contact area between the electrically insulative adhesive tape and the sealing resin for obtaining a high fixing force between the semiconductor chip and the sealing resin.
It is also preferable that each of the first and second side electrically insulative adhesive tapes continuously extends from the )I stitched portions to an outer stripe region over the inner leads, and the outer stripe region is positioned in the vicinity of the chip edge correspondence position so that ain outside edge of the each of the first and second side electrically insulative adhesive tapes is positioned inside of the chip edge correspondence position. If an adhesion force of the electrically zo insulative adhesive tape with the sealing resin is sufficiently strong, there is raised no problem with increase in contact area between the electrically insulative adhesive tape and the sealing resin.
It is also preferable that each of the first and second side electrically insulative adhesive tapes continuously extends from the s- stitched portions to the chip edge correspondence position so that an outside edge of the each of the first and second side electrically insulative adhesive tapes is positioned at the chip edge correspondence position. If an adhesion force of the electrically insulative adhesive tape with the sealing resin is sufficiently strong, there is raised no problem with increase in Si contact area between the electrically insulative adhesive tape and the *sealing resin.
The sixth broad aspect of the present invention provides an electrically insulative adhesive tape extending over stitched portions of inner leads of a lead frame. The inner leads extend substantially in parallel to each other and 3s being aligned in a direction substantially vertical to a longitudinal direction of the inner leads, so that the electrically insulative adhesive tape extends Page 41 on an inner stripe region over the inner leads so as to adhere the stitched portions of the inner leads. The electrically insulative adhesive tape have both surfaces with adhesion force. It is also important that the electrically insulative adhesive tape is further present in at least two positions which are spaced from each other in a direction vertical to the longitudinal direction of the inner leads and which are also located outside of the stitched portions of the inner leads and the two positions are located in the vicinity of chip edge correspondence positions of the inner leads, where the chip edge correspondence position is previously determined to correspond Io to an edge of the semiconductor chip after the semiconductor chip has been adhered to the lead frame by the first and second electrically insulative adhesive tapes.
In accordance with a broad aspect of the present invention, the above lead frame allows that the semiconductor chip andcthe inner leads aligned are fixed by is the electrically insulative adhesive tape at a plurality of positions which are distanced from each other to keep a positional balance of fixing points so as to certainly prevent the any substantive movement of the semiconductor chip particularly in the direction vertical to the surface of the semiconductor chip. Namely, the presence of the electrically insulative 20 adhesive tape at least the two positions spaced from each other in the direction parallel to the center line and which are also located in the vicinity of the edge of the semiconductor chip would result in that inner leads, which extend through the two positions, are fixed not only at the S. stitched portion but also outside portion in the vicinity of the edge of the 25 semiconductor chip. This structure is capable of certainly preventing a substantive movement of the semiconductor chip in a direction vertical to the surface of the semiconductor chip by pressure of the flow of the molten resin when the resin is injected into dies for packaging the semiconductor chip. The certain prevention of the substantive movement of the So semiconductor chip would result ir a certain prevention of the inner leads from being made into contact with the edge of the semiconductor chip. The certain prevention of the substantive movement of the semiconductor chip would also result in a certain prevention of the top portion of the semiconductor device such as tops of bonding wires from exposure from 3s the sealing resin. The certain prevention of the substantive movement of the semiconductor chip would also result in a certain prevention of the Page 42 Pf-2090/nec/Australia/mh bottom portion of the semiconductor device such as bottom surface of the semiconductor chip or the inner leads from exposure from the sealing resin.
The certain prevention of the substantive movement of the semiconductor chip means that the above structure is also capable of keeping a constant distance between the semiconductor chip and the inner lead extending over the semiconductor chip. The certain prevention of the substantive movement of the semiconductor chip also means that the structure is capable of keeping a balance in thickness between upper and lower portions of the sealing resin packaging the semiconductor chip due to no 1o substantive movement nor shift in the direction vertical to the surface of the semiconductor chip. Keeping the balance in thickness between upper and lower portions of the sealing resin prevents formation of any thicknessreduced portion, resulting in a remarkable reduction in the probability in appearance of crack on the thickness-reduced portion of the resin. From the above description, it can be understood that the above novel structure allows a high yield of manufacturing the semiconductor device and also allows the semiconductor device to have a high reliability.
It is preferable that the electrically insulative adhesive tape is further positioned so as to adhere outer-most two of the inner leads.
20 It is further preferable that the outer-most two of the inner leads i" have spread portions which are adhered with the electrically insulative adhesive tape, so as to increase an adhering area between the inner leads and the electrically insulative adhesive tape and decrease an exposed area of the electrically insulative adhesive tape. If an adhesion force of the 2s electrically insulative adhesive tape with the sealing resin is relatively weak, it is particularly effective to reduce the contact area between the electrically insulative adhesive tape and the sealing resin for obtaining a high fixing force between the semiconductor chip and the sealing resin.
It is also preferable that the electrically insulative adhesive tape S.i 3o is further positioned so as to adhere secondly outer two of the inner leads.
It is further preferable that the secondly outer two of the inner leads have spread portions which are adhered with the electrically insulative adhesive tape, so as to increase an adhering area between the inner leads and the electrically insulative adhesive tape and decrease an ,s exposed area of the electrically insulative adhesive tape. If an adhesion force of the electrically insulative adhesive tape with the sealing resin is Page 43 Pf-2090/nec/Australia/mh relatively weak, it is particularly effective to reduce the contact area between the electrically insulative adhesive tape and the sealing resin for obtaining a high fixing force between the semiconductor chip and the sealing resin.
It is also preferable that the electrically insulative adhesive tapes is further positioned so as to adhere outer-most two and secondly outer two of the inner leads.
It is further preferable that the outer-most two and the secondly outer two of the inner leads have spread portions which are adhered with 1o the electrically insulative adhesive tape, so as to increase an adhering area between the inner leads and the electrically insulative adhesive tape and decrease an exposed area of the electrically insulative adhesive tape. If an adhesion force of the electrically insulative adhesive tape with the sealing resin is relatively weak, it is particularly effective to reduce the contact area between the electrically insulative adhesive tape and the sealing resin for obtaining a high fixing force between the semiconductor chip and the sealing resin.
It is also preferable that the electrically insulative adhesive tape is further positioned so as to adhere outer-most one of the inner leads and 20 secondly outer one in an opposite side to the outer-most one.
It is further preferable that the outer-most one of the inner leads and the secondly outer one in an opposite side to the outer-most one of the inner leads have spread portions which are adhered with the electrically insulative adhesive tape, so as to increase an adhering area between the 2G inner leads and the electrically insulative adhesive tape and decrease an exposed area of the electrically insulative adhesive tape. If an adhesion force of the electrically insulative adhesive tape with the sealing resin is 0 ""relatively weak, it is particularly effective to reduce the contact area between the electrically insulative adhesive tape and the sealing resin for .3o obtaining a high fixing force between the semiconductor chip and the 0 00 0sealing resin.
It is also preferable that the electrically insulative adhesive tape further extends on an outer stripe region over the inner leads in the vicinity of the chip edge correspondence positions, where the outer stripe region is positioned outside of and separated from the stitched portion, and an outside edge of the each of the first and second side electrically insulative Page 44 Pf-2090/nec/Australia/mh adhesive tapes is positioned inside of the chip edge correspondence position.
It is further preferable that the inner leads have spread portions which are adhered with the electrically insulative adhesive tape, provided that the spread portions of the adjacent two of the inner leads are separated from each other, so as to increase an adhering area between the inner leads and, the electrically insulative adhesive tape and decrease an exposed area of the electrically insulative adhesive tape. If an adhesion force of the electrically insulative adhesive tape with the sealing resin is relatively weak, to it is particularly effective to reduce the contact area between the electrically insulative adhesive tape and the sealing resin for obtaining a high fixing force between the semiconductor chip and the sealing resin.
It is also preferable that the electrically insulative adhesive tape further extends on an outer stripe region over the inner leads in the vicinity ,G of the chip edge correspondence positions, where the outer stripe region is positioned outside of and separated from the stitched portion, and an outside edge of the electrically insulative adhesive tape is positioned at the chip edge correspondence position.
It is further preferable that the inner leads have spread portions 2o which are adhered with the electrically insulative adhesive tape, provided that the spread portions of the adjacent two of the inner leads are separated from each other, so as to increase an adhering area between the inner leads and the electrically insulative adhesive tape and decrease an exposed area of the electrically insulative adhesive tape. If an adhesion force of the S 2- electrically insulative adhesive tape with the sealing resin is relatively weak, it is particularly effective to reduce the contact area between the electrically >insulative adhesive tape and the sealing resin for obtaining a high fixing forcebetween the semiconductor chip and the sealing resin.
It is also preferable that the electrically insulative adhesive tape 0 continuously extends from the stitched portions to an outer stripe region over the inner leads, and the outer stripe region is positioned in the vicinity of the chip edge correspondence position so that an outside edge of the electrically insulative adhesive tape is positioned inside of the chip edge correspondence position. If an adhesion force of the electrically insulative 3s- adhesive tape with the sealing resin is sufficiently strong, there is raised no problem with increase in contact area between the electrically insulative Page Pf-2090/nec/Australia/mh adhesive tape and the sealing resin.
It is also preferable that the electrically insulative adhesive tape continuously extends from the stitched portions to the chip edge correspondence position so that an outside edge of the electrically insulative adhesive tape is positioned at the chip edge correspondence position. If an adhesion force of the electrically insulative adhesive tape with the sealing resin is sufficiently strong, there is raised no problem with increase in contact area between the electrically insulative adhesive tape and the sealing resin.
0o PREFERRED EMBODIMENTS FIRST EMBODIMENT: A first embodiment according to the present invention will be described in detail with reference to FIGS. 6, 7, 8, 9 and 10, wherein a novel lead-on-chip structure of a semiconductor is provided. FIG. 6 is a 1s- fragmentary plane view illustrative of a novel lead-on-chip structure of a semiconductor device. FIG. 7 is a fragmentary cross sectional elevation view illustrative of a novel lead-on-chip structure of a semiconductor device. FIG. 8 is a fragmentary cross sectional elevation view illustrative of a novel lead-on-chip structure semiconductor device packaged with a 2o sealing resin wherein a semiconductor chip had received up-force by a molten resin when the resin was injected into dies in a first embodiment in accordance with the present invention. FIG. 9 is a fragmentary cross sectional elevation view illustrative of a novel lead-on-chip structure semiconductor device packaged with a sealing resin wherein a 25. semiconductor chip had received down-force by a molten resin when the resin was injected into dies. FIG. 10 is a fragmentary cross sectional elevation view illustrative of an electrically insulative adhesive tape to be used for adhering a semiconductor chip to inner leads.
The lead-on-chip structure comprises the following elements. A 2o semiconductor chip 4 has a top surface which further has two alignments of bonding pads along opposite sides of a center line of the semiconductor chip 4. The center line separates the semiconductor chip 4 into first (left) and second (right) side regions. First and second alignments of inner leads 1 extend over the first and second side regions of the semiconductor chip 4 Q) Page 46 Pf-2090/nec/Australia/mh respectively so that the inner leads 1 are spaced from the top surface of the semiconductor chip 4. The inner leads 1 have stitched portions 2 positioned in inside terminal portions thereof. The stitched portions 2 of the inner leads 1 are positioned outside of the bonding pads. The inner leads 1 extend substantially in parallel to each other and along a direction vertical to the center line of the semiconductor chip 4. Bonding wires 5 electrically connect the stitched portions 2 of the inner leads 1 to corresponding ones of the bonding pads of the semiconductor chip 4.
First (left) and second (right) side electrically insulative adhesive 1o inner tapes 3A are provided for adhering the semiconductor chip 4 to the stitched portions of the inner leads 1. Each of the electrically insulative adhesive inner tapes 3A has top and bottom surfaces with adhesion force.
For example, it may be possible as illustrated in FIG. 10, that the electrically insulative adhesive inner tape 3A may comprise a sandwich is- multi-layer structure of a base material layer 9 which has a high flexibility sandwiched between adhesive layers 8. Alternatively, a single layered structure is also available provided that the tape has a sufficient adhesive force. The bottom surfaces of the first and second side electrically insulative adhesive inner tapes 3A are adhered onto first and second inner 2o stripe regions of the semiconductor chip 4 in the process for adhering the semiconductor chip onto the inner leads 1 of a lead frame. The first and second inner stripe regions are positioned outside of the bonding pads. The top surfaces of the first and second side electrically insulative adhesive inner tapes 3A have previously been adhered on bottom surfaces of the 2- stitched portions 2 of the inner leads 1 before the process for adhering the semiconductor chip onto the inner leads 1 of a lead frame.
For the present invention, it is also important that first and second side electrically insulative adhesive outer tapes 3B are further provided which extend on outer stripe regions in the vicinity of and in 8o parallel to opposite edges of the semiconductor chip 4, where the outer stripe regions are separated from the inner stripe regions. An outside edge of each of the first and second side electrically insulative adhesive outer tapes 3B is positioned slightly inside of the edge of the semiconductor chip 4, so that the inner leads 1 are fixed not only in the stitched portions 2 but Ss also outer positions in the vicinity of the edge of the semiconductor chip 4.
In accordance with the present invention, the semiconductor chip Page 47 Pf-2090/nec/Australia/mh 4 and, the inner leads 1 aligned are fixed by the electrically insulative adhesive tapes at a plurality of positions which are distanced from each other to keep a positional balance of fixing points so as to certainly prevent the any substantive movement of the semiconductor chip 4 particularly in the direction vertical to the surface of the semiconductor chip 4.
Namely, the presence of the electrically insulative adhesive outer tapes 3B would result in that inner leads 1 are fixed not only at the stitched portions 2 but also outside portions in the vicinity of the edges of the semiconductor chip 4. This structure is capable of certainly preventing a io substantive movement of the semiconductor chip 4 in a direction vertical to the surface of the semiconductor chip 4 by pressure of the flow of the molten resin when the resin is injected into dies for packaging the semiconductor chip 4. The certain prevention of the substantive movement of the semiconductor chip 4 would result in a certain prevention of the 1& inner leads 1 from being made into contact with the edges of the semiconductor chip 4. The certain prevention of the substantive movement of the semiconductor chip 4 would also result in a certain prevention of the top portion of the semiconductor device such as tops of bonding wires from exposure from the sealing resin or a package 6. The certain prevention of o the substantive movement of the semiconductor chip 4 would also result in a certain prevention of the bottom portion of the semiconductor device such as the bottom surface of the semiconductor chip 4 from exposure from the sealing resin or the package 6. The certain prevention of the substantive movement of the semiconductor chip 4 means that the above structure is 2s- also capable of keeping a constant distance between the semiconductor chip 4 and the inner lead 1 extending over the semiconductor chip 4. The certain prevention of the substantive movement of the semiconductor chip 4 also means that the structure is capable of keeping a balance in thickness between upper and lower portions of the sealing resin 6 for packaging the 3o semiconductor chip 4 due to no substantive movement nor shift in the direction vertical to the surface of the semiconductor chip 4. Keeping the balance in thickness between upper and lower portions of the sealing resin 6. prevents formation of any thickness-reduced portion of the sealing resin 6, resulting in a remarkable reduction in the probability in appearance of crack on the thickness-reduced portion of the resin 6. From the above description, it can be understood that the above novel structure allows a Q) Page 48 Pf-2090/nec/Australia/mh high yield of manufacturing the semiconductor device and also allows the semiconductor device to have a high reliability.
SECOND EMBODIMENT: A second embodiment according to the present invention will be s- described in detail with reference to FIG. 11, wherein a novel lead-on-chip structure of a semiconductor is provided. FIG. 11 is a fragmentary plane view illustrative of a novel lead-on-chip structure of a semiconductor device.
The lead-on-chip structure comprises the following elements. A 1o semiconductor chip 4 has a top surface which further has two alignments of bonding pads along opposite sides of a center line of the semiconductor chip 4. The center line separates the semiconductor chip 4 into first (left) and second (right) side regions. First and second alignments of inner leads 1 extend over the first and second side regions of the semiconductor chip 4 respectively so that the inner leads 1 are spaced from the top surface of the semiconductor chip 4. The inner leads 1 have stitched portions 2 positioned in inside terminal portions thereof. The stitched portions 2 of the inner leads 1 are positioned outside of the bonding pads. The inner leads 1 extend substantially in parallel to each other and along a direction vertical to the 20 center line of the semiconductor chip 4. Bonding wires 5 electrically connect the stitched portions 2 of the inner leads 1 to corresponding ones of the bonding pads of the semiconductor chip 4.
First (left) and second (right) side electrically insulative adhesive inner tapes 3A are provided for adhering the semiconductor chip 4 to the zS- stitched portions of the inner leads 1. Each of the electrically insulative adhesive inner tapes 3A has top and bottom surfaces with adhesion force.
For example, it may be possible as illustrated in FIG. 10, that the electrically insulative adhesive inner tape 3A may comprise a sandwich So.: multi-layer structure of a base material layer 9 which has a high flexibility 3o sandwiched between adhesive layers 8. Alternatively, a single layered structure is also available provided that the tape has a sufficient adhesive force. The bottom surfaces of the first and second side electrically insulative adhesive inner tapes 3A are adhered onto first and second inner stripe regions of the semiconductor chip 4 in the process for adhering the semiconductor chip onto the inner leads 1 of a lead frame. The first and Page 49 Pf-2090/nec/Australia/mh second inner stripe regions are positioned outside of the bonding pads. The top surfaces of the first and second side electrically insulative adhesive inner tapes 3A have previously been adhered on bottom surfaces of the stitched portions 2 of the inner leads 1 before the process for adhering the s- semiconductor chip onto the inner leads 1 of a lead frame.
For the present invention, it is also important that first and second side electrically insulative adhesive outer tapes 3B are further provided which extend on outer stripe regions in the vicinity of and in parallel to opposite edges of the semiconductor chip 4, where the outer 1o stripe regions are separated from the inner stripe regions. An outside edge of each of the first and second side electrically insulative adhesive outer tapes 3B is positioned slightly inside of the edge of the semiconductor chip 4, so that the inner leads 1 are fixed not only in the stitched portions 2 but also outer positions in the vicinity of the edge of the semiconductor chip 4.
I Each of the electrically insulative adhesive outer tapes 3B has top and bottom surfaces with adhesion force. For example, it may be possible as illustrated in FIG. 10, that the electrically insulative adhesive outer tape 3B may comprise a sandwich multi-layer structure of a base material layer 9 which has a high flexibility sandwiched between adhesive layers 8.
2o Alternatively, a single layered structure is also available provided that the tape has a sufficient adhesive force.
Further, the inner leads 1 have spread portions 7 which are adhered with the electrically insulative adhesive outer tape 3B. The spread portions 7 of the adjacent two of the inner leads 1 are separated from each 25 other, so as to increase an adhering area between the inner leads 1 and the electrically insulative adhesive outer tape 3B and decrease a contact area between the electrically insulative adhesive outer tape 3b with the sealing S.resin material 6 for packaging the semiconductor chip 4. If an adhesion force of the electrically insulative adhesive tapes 3A and 3B with the ~So sealing resin 6 is relatively weak, it is particularly effective to reduce the contact area between the electrically insulative adhesive tapes 3A and 3B and the sealing resin 6 for obtaining a high fixing force between the semiconductor chip 4 and the sealing resin 6.
In accordance with the present invention, the semiconductor chip 3s- 4 and the inner leads 1 aligned are fixed by the electrically insulative adhesive tapes at a plurality of positions which are distanced from each Page Pf-2090/nec/Australia/mh other to keep a positional balance of fixing points so as to certainly prevent the any substantive movement of the semiconductor chip 4 particularly in the direction vertical to the surface of the semiconductor chip 4.
Namely, the presence of the electrically insulative adhesive outer tapes 3B would result in that inner leads 1 are fixed not only at the stitched portions 2 but also outside portions in the vicinity of the edges of the semiconductor chip 4. This structure is capable of certainly preventing a substantive movement of the semiconductor chip 4 in a direction vertical to the surface of the semiconductor chip 4 by pressure of the flow of the molten resin when the resin is injected into dies for packaging the semiconductor chip 4. The certain prevention of the substantive movement of the semiconductor chip 4 would result in a certain prevention of the inner leads 1 from being made into contact with the edges of the semiconductor chip 4. The certain prevention of the substantive movement Is of the semiconductor chip 4 would also result in a certain prevention of the top portion of the semiconductor device such as tops of bonding wires from exposure from the sealing resin or a package 6. The certain prevention of the substantive movement of the semiconductor chip 4 would also result in a certain prevention of the bottom portion of the semiconductor device such 2 as the bottom surface of the semiconductor chip 4 from exposure from the sealing resin or the package 6. The certain prevention of the substantive L.'":movement of the semiconductor chip 4 means that the above structure is also capable of keeping a constant distance between the semiconductor chip 4 and the inner lead 1 extending over the semiconductor chip 4. The certain prevention of the substantive movement of the semiconductor chip 4 also means that the structure is capable of keeping a balance in thickness between upper and lower portions of the sealing resin 6 for packaging the semiconductor chip 4 due to no substantive movement nor shift in the direction vertical to the surface of the semiconductor chip 4. Keeping the 3o balance in thickness between upper and lower portions of the sealing resin 6 prevents formation of any thickness-reduced portion of the sealing resin 6, resulting in a remarkable reduction in the probability in appearance of crack on the thickness-reduced portion of the resin 6. From the above description, it can be understood that the above novel structure allows a gs high yield of manufacturing the semiconductor device and also allows the semiconductor device to have a high reliability.
Page 51 Pf-2090/nec/Australia/mh THIRD EMBODIMENT: A third embodiment according to the present invention will be described in detail with reference to FIGS. 12, 13, 14, 15 and 10, wherein a novel lead-on-chip structure of a semiconductor is provided. FIG. 12 is a s fragmentary plane view illustrative of a novel lead-on-chip structure of a semiconductor device. FIG. 13 is a fragmentary cross sectional elevation view illustrative of a novel lead-on-chip structure of a semiconductor device. FIG. 14 is a fragmentary cross sectional elevation view illustrative of. a novel lead-on-chip structure semiconductor device packaged with a o sealing resin wherein a semiconductor chip had received up-force by a molten resin when the resin was injected into dies in a first embodiment in accordance with the present invention. FIG. 15 is a fragmentary cross sectional elevation view illustrative of a novel lead-on-chip structure semiconductor device packaged with a sealing resin wherein a S semiconductor chip had received down-force by a molten resin when the resin was injected into dies. FIG. 10 is a fragmentary cross sectional elevation view illustrative of an electrically insulative adhesive tape to be used for adhering a semiconductor chip to inner leads.
The lead-on-chip structure comprises the following elements. A 20 semiconductor chip 4 has a top surface which further has two alignments of bonding pads along opposite sides of a center line of the semiconductor chip 4. The center line separates the semiconductor chip 4 into first (left) and second (right) side regions. First and second alignments of inner leads S"1 extend over the first and second side regions of the semiconductor chip 4 respectively so that the inner leads 1 are spaced from the top surface of the semiconductor chip 4. The inner leads 1 have stitched portions 2 positioned S.in inside terminal portions thereof. The stitched portions 2 of the inner leads 1 are positioned outside of the bonding pads. The inner leads 1 extend .S substantially in parallel to each other and along a direction vertical to the 0 center line of the semiconductor chip 4. Bonding wires 5 electrically connect the stitched portions 2 of the inner leads 1 to corresponding ones of the bonding pads of the semiconductor chip 4.
First (left) and second (right) side electrically insulative adhesive inner tapes 3A are provided for adhering the semiconductor chip 4 to the 3S stitched portions of the inner leads 1. Each of the electrically insulative 0 Page 52 Pf-2090/nec/Australialmh adhesive inner tapes 3A has top and bottom surfaces with adhesion force.
For example, it may be possible as illustrated in FIG. 10, that the electrically insulative adhesive inner tape 3A may comprise a sandwich multi-layer structure of a base material layer 9 which has a high flexibility sandwiched between adhesive layers 8. Alternatively, a single layered structure is also available provided that the tape has a sufficient adhesive force. The bottom surfaces of the first and second side electrically insulative adhesive inner tapes 3A are adhered onto first and second inner stripe regions of the semiconductor chip 4 in the process for adhering the Io semiconductor chip onto the inner leads 1 of a lead frame. The first and second inner stripe regions are positioned outside of the bonding pads. The top surfaces of the first and second side electrically insulative adhesive inner tapes 3A have previously been adhered on bottom surfaces of the stitched portions 2 of the inner leads 1 before the process for adhering the Is- semiconductor chip onto the inner leads 1 of a lead frame.
For the present invention, it is also important that first and second side electrically insulative adhesive outer tapes 3B are further provided which extend on outer stripe regions in the vicinity of and in 0parallel to opposite edges of the semiconductor chip 4, where the outer 20 stripe regions are separated from the inner stripe regions. An outside edge of each of the first and second side electrically insulative adhesive outer :,bestapes 3B is positioned in correspondence to the edge of the semiconductor chip 4, so that the inner leads 1 are fixed not only in the stitched portions 2 0but also outer positions at the edge of the semiconductor chip 4.
2s- In accordance with the present invention, the semiconductor chip 4 and the inner leads 1 aligned are fixed by the electrically insulative adhesive tapes at a plurality of positions which are distanced from each other to keep a positional balance of fixing points so as to certainly prevent the any substantive movement of the semiconductor chip 4 particularly in ?o the direction vertical to the surface of the semiconductor chip 4.
Namely, the presence of the electrically insulative adhesive outer tapes 3B would result in that inner leads 1 are fixed not only at the stitched portions 2 but also outside portions at the edges of the semiconductor chip 4. This structure is capable of certainly preventing a substantive movement 3s of the semiconductor chip 4 in a direction vertical to the surface of the semiconductor chip 4 by pressure of the flow of the molten resin when the O Page 53 Pf-2090/nec/Australia/mh resin is injected into dies for packaging the semiconductor chip 4. The certain prevention of the substantive movement of the semiconductor chip 4 would result in a certain prevention of the inner leads 1 from being made into contact with the edges of the semiconductor chip 4. The certain prevention of the substantive movement of the semiconductor chip 4 would also result in a certain prevention of the top portion of the semiconductor device such as tops of bonding wires from exposure from the sealing resin or a package 6. The certain prevention of the substantive movement of the semiconductor chip 4 would also result in a certain prevention of the bottom portion of the semiconductor device such as the bottom surface of the semiconductor chip 4 from exposure from the sealing resin or the package 6. The certain prevention of the substantive movement of the semiconductor chip 4 means that the above structure is also capable of keeping a constant distance between the semiconductor chip 4 and the inner is- lead 1 extending over the semiconductor chip 4. The certain prevention of the substantive movement of the semiconductor chip 4 also means that the structure is capable of keeping a balance in thickness between upper and lower portions of the sealing resin 6 for packaging the semiconductor chip due to no substantive movement nor shift in the direction vertical to the 20 surface of the semiconductor chip 4. Keeping the balance in thickness between upper and lower portions of the sealing resin 6 prevents formation of any thickness-reduced portion of the sealing resin 6, resulting in a remarkable reduction in the probability in appearance of crack on the thickness-reduced portion of the resin 6. From the above description, it can s- be understood that the above novel structure allows a high yield of manufacturing the semiconductor device and also allows the semiconductor S. device to have a high reliability.
&too FOURTH EMBODIMENT: A fourth embodiment according to the present invention will be 3o described in detail with reference to FIG. 16, wherein a novel lead-on-chip structure of a semiconductor is provided. FIG. 16 is a fragmentary plane view illustrative of a novel lead-on-chip structure of a semiconductor device.
The lead-on-chip structure comprises the following elements. A 3s semiconductor chip 4 has a top surface which further has two alignments of 0 Page 54 Pf-2090/nec/Australia/mh bonding pads along opposite sides of a center line of the semiconductor chip 4. The center line separates the semiconductor chip 4 into first (left) and second (right) side regions. First and second alignments of inner leads 1 extend over the first and second side regions of the semiconductor chip 4 respectively so that the inner leads 1 are spaced from the top surface of the semiconductor chip 4. The inner leads 1 have stitched portions 2 positioned in inside terminal portions thereof. The stitched portions 2 of the inner leads 1 are positioned outside of the bonding pads. The inner leads 1 extend substantially in parallel to each other and along a direction vertical to the io center line of the semiconductor chip 4. Bonding wires 5 electrically connect the stitched portions 2 of the inner leads 1 to corresponding ones of the bonding pads of the semiconductor chip 4.
First (left) and second (right) side electrically insulative adhesive inner tapes 3A are provided for adhering the semiconductor chip 4 to the stitched portions of the inner leads 1. Each of the electrically insulative adhesive inner tapes 3A has top and bottom surfaces with adhesion force.
For, example, it may be possible as illustrated in FIG. 10, that the electrically insulative adhesive inner tape 3A may comprise a sandwich multi-layer structure of a base material layer 9 which has a high flexibility 2-o" 0 c sandwiched between adhesive layers 8. Alternatively, a single layered oo structure is also available provided that the tape has a sufficient adhesive °oo force. The bottom surfaces of the first and second side electrically insulative adhesive inner tapes 3A are adhered onto first and second inner stripe regions of the semiconductor chip 4 in the process for adhering the Ssemiconductor chip onto the inner leads 1 of a lead frame. The first and second inner stripe regions are positioned outside of the bonding pads. The top surfaces of the first and second side electrically insulative adhesive inner tapes 3A have previously been adhered on bottom surfaces of the stitched portions 2 of the inner leads 1 before the process for adhering the Zo semiconductor chip onto the inner leads 1 of a lead frame.
i For the present invention, it is also important that first and second side electrically insulative adhesive outer tapes 3B are further provided which extend on outer stripe regions in the vicinity of and in parallel to opposite edges of the semiconductor chip 4, where the outer stripe regions are separated from the inner stripe regions. An outside edge of each of the first and second side electrically insulative adhesive outer no Page Pf-2090/nec/Australia/mh tapes 3B is positioned at the edge of the semiconductor chip 4, so that the inner leads 1 are fixed not only in the stitched portions 2 but also outer positions at the edge of the semiconductor chip 4.
Each of the electrically insulative adhesive outer tapes 3B has top S- and bottom surfaces with adhesion force. For example, it may be possible as illustrated in FIG. 10, that the electrically insulative adhesive outer tape 3B. may comprise a sandwich multi-layer structure of a base material layer 9 which has a high flexibility sandwiched between adhesive layers 8.
Alternatively, a single layered structure is also available provided that the (o tape has a sufficient adhesive force.
Further, the inner leads 1 have spread portions 7 which are adhered with the electrically insulative adhesive outer tape 3B. The spread portions 7 of the adjacent two of the inner leads 1 are separated from each other, so as to increase an adhering area between the inner leads 1 and the Is electrically insulative adhesive outer tape 3B and decrease a contact area between the electrically insulative adhesive outer tape 3b with the sealing resin material 6 for packaging the semiconductor chip 4. If an adhesion force of the electrically insulative adhesive tapes 3A and 3B with the sealing resin 6 is relatively weak, it is particularly effective to reduce the Ie 2o contact area between the electrically insulative adhesive tapes 3A and 3B °o and the sealing resin 6 for obtaining a high fixing force between the semiconductor chip 4 and the sealing resin 6.
-In accordance with the present invention, the semiconductor chip 4 and the inner leads 1 aligned are fixed by the electrically insulative adhesive tapes at a plurality of positions which are distanced from each other to keep a positional balance of fixing points so as to certainly prevent the any substantive movement of the semiconductor chip 4 particularly in the direction vertical to the surface of the semiconductor chip 4.
SNamely, the presence of the electrically insulative adhesive outer o tapes 3B would result in that inner leads 1 are fixed not only at the stitched portions 2 but also outside portions at the edges of the semiconductor chip 4. This structure is capable of certainly preventing a substantive movement of the semiconductor chip 4 in a direction vertical to the surface of the semiconductor chip 4 by pressure of the flow of the molten resin when the resin is injected into dies for packaging the semiconductor chip 4. The certain prevention of the substantive movement of the semiconductor chip 0 Page 56 Pf-2090/nec/Australia/mh 4 would result in a certain prevention of the inner leads 1 from being made into contact with the edges of the semiconductor chip 4. The certain prevention of the substantive movement of the semiconductor chip 4 would also result in a certain prevention of the top portion of the semiconductor device such as tops of bonding wires from exposure from the sealing resin or a package 6. The certain prevention of the substantive movement of the semiconductor chip 4 would also result in a certain prevention of the bottom portion of the semiconductor device such as the bottom surface of the, semiconductor chip 4 from exposure from the sealing resin or the 1o package 6. The certain prevention of the substantive movement of the semiconductor chip 4 means that the above structure is also capable of keeping a constant distance between the semiconductor chip 4 and the inner lead 1 extending over the semiconductor chip 4. The certain prevention of the. substantive movement of the semiconductor chip 4 also means that the 1s structure is capable of keeping a balance in thickness between upper and lower portions of the sealing resin 6 for packaging the semiconductor chip 4 due to no substantive movement nor shift in the direction vertical to the surface of the semiconductor chip 4. Keeping the balance in thickness between upper and lower portions of the sealing resin 6 prevents formation 2o of any thickness-reduced portion of the sealing resin 6, resulting in a oe remarkable reduction in the probability in appearance of crack on the thickness-reduced portion of the resin 6. From the above description, it can be understood that the above novel structure allows a high yield of manufacturing the semiconductor device and also allows the semiconductor device to have a high reliability.
FIFTH EMBODIMENT: A fifth embodiment according to the present invention will be described in detail with reference to FIGS. 17, 18, 19, 20 and 10, wherein a novel lead-on-chip structure of a semiconductor is provided. FIG. 17 is a fragmentary plane view illustrative of a novel lead-on-chip structure of a semiconductor device. FIG. 18 is a fragmentary cross sectional elevation view illustrative of a novel lead-on-chip structure of a semiconductor device. FIG. 19 is a fragmentary cross sectional elevation view illustrative of a novel lead-on-chip structure semiconductor device packaged with a 3s sealing resin wherein a semiconductor chip had received up-force by a C0 Page 5 7 Pf-2090/nec/Australia/mh molten resin when the resin was injected into dies in a first embodiment in accordance with the present invention. FIG. 20 is a fragmentary cross sectional elevation view illustrative of a novel lead-on-chip structure semiconductor device packaged with a sealing resin wherein a semiconductor chip had received down-force by a molten resin when the resin was injected into dies.
The lead-on-chip structure comprises the following elements. A semiconductor chip 4 has a top surface which further has two alignments of banding pads along opposite sides of a center line of the semiconductor lo chip 4. The center line separates the semiconductor chip 4 into first (left) and second (right) side regions. First and second alignments of inner leads 1 extend over the first and second side regions of the semiconductor chip 4 respectively so that the inner leads 1 are spaced from the top surface of the semiconductor chip 4. The inner leads 1 have stitched portions 2 positioned i in inside terminal portions thereof. The stitched portions 2 of the inner leads 1 are positioned outside of the bonding pads. The inner leads 1 extend substantially in parallel to each other and along a direction vertical to the center line of the semiconductor chip 4. Bonding wires 5 electrically connect the stitched portions 2 of the inner leads 1 to corresponding ones of 2°o o the bonding pads of the semiconductor chip 4.
°o First (left) and second (right) side electrically insulative adhesive ooinner tapes 3A are provided for adhering the semiconductor chip 4 to the stitched portions of the inner leads 1. Each of the electrically insulative adhesive inner tapes 3A has top and bottom surfaces with adhesion force.
'ooo 2s For example, it may be possible as illustrated in FIG. 10, that the electrically insulative adhesive inner tape 3A may comprise a sandwich multi-layer structure of a base material layer 9 which has a high flexibility sandwiched between adhesive layers 8. Alternatively, a single layered structure is also available provided that the tape has a sufficient adhesive force. The bottom surfaces of the first and second side electrically insulative adhesive inner tapes 3A are adhered onto first and second inner stripe regions of the semiconductor chip 4 in the process for adhering the semiconductor chip onto the inner leads 1 of a lead frame. The first and second inner stripe regions are positioned outside of the bonding pads. The top surfaces of the first and second side electrically insulative adhesive inner tapes 3A have previously been adhered on bottom surfaces of the C0 Page 58 Pf-2090/nec!Australia/mh stitched portions 2 of the inner leads 1 before the process for adhering the semiconductor chip onto the inner leads 1 of a lead frame.
For the present invention, it is also important that first and second side electrically insulative adhesive outer tapes 3B are selectively provided which reside in the vicinity of four corners of the semiconductor chip 4 to adhere only outer-most two of the inner leads 1 in the vicinity of the edges of the semiconductor chip 4. An outside edge of each of the first and second side electrically insulative adhesive outer tapes 3B is positioned slightly inside of the edge of the semiconductor chip 4, so that the outero most two of the inner leads 1 are fixed not only in the stitched portions 2 but also outer positions in the vicinity of the edge of the semiconductor chip 4.
In accordance with the present invention, the semiconductor chip 4 and the inner leads 1 aligned are fixed by the electrically insulative is adhesive tapes at a plurality of positions which are distanced from each other to keep a positional balance of fixing points so as to certainly prevent the any substantive movement of the semiconductor chip 4 particularly in the direction vertical to the surface of the semiconductor chip 4.
Namely, the presence of the electrically insulative adhesive outer 2 tapes 3B would result in that the outer-most two of the inner leads 1 are fixed not only at the stitched portions 2 but also outside portions in the "'"'"vicinity of the edges of the semiconductor chip 4. This structure is capable of certainly preventing a substantive movement of the semiconductor chip 4 in a direction vertical to the surface of the semiconductor chip 4 by o pressure of the flow of the molten resin when the resin is injected into dies for packaging the semiconductor chip 4. The certain prevention of the substantive movement of the semiconductor chip 4 would result in a certain prevention of the inner leads 1 from being made into contact with the edges of the semiconductor chip 4. The certain prevention of the substantive &o movement of the semiconductor chip 4 would also result in a certain e prevention of the top portion of the semiconductor device such as tops of bonding wires from exposure from the sealing resin or a package 6. The certain prevention of the substantive movement of the semiconductor chip 4 would also result in a certain prevention of the bottom portion of the 3- semiconductor device such as the bottom surface of the semiconductor chip 4 from exposure from the sealing resin or the package 6. The certain Page 59 Pf-2090/nec/Australia/mh prevention of the substantive movement of the semiconductor chip 4 means that the above structure is also capable of keeping a constant distance between the semiconductor chip 4 and the inner lead 1 extending over the semiconductor chip 4. The certain prevention of the substantive movement s- of the semiconductor chip 4 also means that the structure is capable of keeping a balance in thickness between upper and lower portions of the sealing resin 6 for packaging the semiconductor chip 4 due to no substantive movement nor shift in the direction vertical to the surface of the semiconductor chip 4. Keeping the balance in thickness between upper and So lower portions of the sealing resin 6 prevents formation of any thicknessreduced portion of the sealing resin 6, resulting in a remarkable reduction in the probability in appearance of crack on the thickness-reduced portion of the resin 6. From the above description, it can be understood that the above novel structure allows a high yield of manufacturing the is semiconductor device and also allows the semiconductor device to have a high reliability.
SIXTH EMBODIMENT: A sixth embodiment according to the present invention will be .described in detail with reference to FIGS. 21 and 10, wherein a novel leadon-chip structure of a semiconductor is provided. FIG. 21 is a fragmentary :'"'plane view illustrative of a novel lead-on-chip structure of a semiconductor device.
The lead-on-chip structure comprises the following elements. A o semiconductor chip 4 has a top surface which further has two alignments of 2 bonding pads along opposite sides of a center line of the semiconductor chip 4. The center line separates the semiconductor chip 4 into first (left) and second (right) side regions. First and second alignments of inner leads 1 extend over the first and second side regions of the semiconductor chip 4 respectively so that the inner leads 1 are spaced from the top surface of the ****semiconductor chip 4. The inner leads 1 have stitched portions 2 positioned in. inside terminal portions thereof. The stitched portions 2 of the inner leads 1 are positioned outside of the bonding pads. The inner leads 1 extend substantially in parallel to each other and along a direction vertical to the center line of the semiconductor chip 4. Bonding wires 5 electrically connect the stitched portions 2 of the inner leads 1 to corresponding ones of 0 0 Page Pf-2090/nec/Australia/mh the bonding pads of the semiconductor chip 4.
First (left) and second (right) side electrically insulative adhesive inner tapes 3A are provided for adhering the semiconductor chip 4 to the stitched portions of the inner leads 1. Each of the electrically insulative s adhesive inner tapes 3A has top and bottom surfaces with adhesion force.
For example, it may be possible as illustrated in FIG. 10, that the electrically insulative adhesive inner tape 3A may comprise a sandwich multi-layer structure of a base material layer 9 which has a high flexibility sandwiched between adhesive layers 8. Alternatively, a single layered lo structure is also available provided that the tape has a sufficient adhesive force. The bottom surfaces of the first and second side electrically insulative adhesive inner tapes 3A are adhered onto first and second inner stripe regions of the semiconductor chip 4 in the process for adhering the semiconductor chip onto the inner leads 1 of a lead frame. The first and second inner stripe regions are positioned outside of the bonding pads. The top surfaces of the first and second side electrically insulative adhesive inner tapes 3A have previously been adhered on bottom surfaces of the stitched portions 2 of the inner leads 1 before the process for adhering the semiconductor chip onto the inner leads 1 of a lead frame.
ol 20 For the present invention, it is also important that first and second side electrically insulative adhesive outer tapes 3B are selectively :'"'provided which reside in the vicinity of four corners of the semiconductor chip 4 to adhere only second outer two of the inner leads 1 in the vicinity of the edges of the semiconductor chip 4. An outside edge of each of the first and second side electrically insulative adhesive outer tapes 3B is positioned slightly inside of the edge of the semiconductor chip 4, so that the second outer two of the inner leads 1 are fixed not only in the stitched portions 2 but also outer positions in the vicinity of the edge of the semiconductor chip 4.
In accordance with the present invention, the semiconductor chip 4 and the inner leads 1 aligned are fixed by the electrically insulative adhesive tapes at a plurality of positions which are distanced from each other to keep a positional balance of fixing points so as to certainly prevent the, any substantive movement of the semiconductor chip 4 particularly in 3- the direction vertical to the surface of the semiconductor chip 4.
Namely, the presence of the electrically insulative adhesive outer nc Page 61 Pf-2090/nec/Australia/mh tapes 3B would result in that the second outer two of the inner leads 1 are fixed not only at the stitched portions 2 but also outside portions in the vicinity of the edges of the semiconductor chip 4. This structure is capable of certainly preventing a substantive movement of the semiconductor chip S4 in a direction vertical to the surface of the semiconductor chip 4 by pressure of the flow of the molten resin when the resin is injected into dies for packaging the semiconductor chip 4. The certain prevention of the substantive movement of the semiconductor chip 4 would result in a certain prevention of the inner leads 1 from being made into contact with the edges ,o of the semiconductor chip 4. The certain prevention of the substantive movement of the semiconductor chip 4 would also result in a certain prevention of the top portion of the semiconductor device such as tops of bonding wires from exposure from the sealing resin or a package 6. The certain prevention of the substantive movement of the semiconductor chip 's 4 would also result in a certain prevention of the bottom portion of the semiconductor device such as the bottom surface of the semiconductor chip 4 from exposure from the sealing resin or the package 6. The certain prevention of the substantive movement of the semiconductor chip 4 means that the above structure is also capable of keeping a constant distance 2o between the semiconductor chip 4 and the inner lead 1 extending over the semiconductor chip 4. The certain prevention of the substantive movement of the semiconductor chip 4 also means that the structure is capable of :keeping a balance in thickness between upper and lower portions of the sealing resin 6 for packaging the semiconductor chip 4 due to no 2S substantive movement nor shift in the direction vertical to the surface of the ''"semiconductor chip 4. Keeping the balance in thickness between upper and lower portions of the sealing resin 6 prevents formation of any thicknessreduced portion of the sealing resin 6, resulting in a remarkable reduction in the probability in appearance of crack on the thickness-reduced portion -0 of the resin 6. From the above description, it can be understood that the °"above novel structure allows a high yield of manufacturing the semiconductor device and also allows the semiconductor device to have a high reliability.
SEVENTH EMBODIMENT: A seventh embodiment according to the present invention will be O O Page 62 Pf-2090/nec/Australia/mh described in detail with reference to FIGS. 22, 23, 24, 25 and 10, wherein a novel lead-on-chip structure of a semiconductor is provided. FIG. 22 is a fragmentary plane view illustrative of a novel lead-on-chip structure of a semiconductor device. FIG. 23 is a fragmentary cross sectional elevation view illustrative of a novel lead-on-chip structure of a semiconductor device. FIG. 24 is a fragmentary cross sectional elevation view illustrative of a novel lead-on-chip structure semiconductor device packaged with a sealing resin wherein a semiconductor chip had received up-force by a molten resin when the resin was injected into dies in a first embodiment in to accordance with the present invention. FIG. 25 is a fragmentary cross sectional elevation view illustrative of a novel lead-on-chip structure semiconductor device packaged with a sealing resin wherein a semiconductor chip had received down-force by a molten resin when the resin was injected into dies.
I The lead-on-chip structure comprises the following elements. A semiconductor chip 4 has a top surface which further has two alignments of bonding pads along opposite sides of a center line of the semiconductor chip 4. The center line separates the semiconductor chip 4 into first (left) and second (right) side regions. First and second alignments of inner leads 2o 1 extend over the first and second side regions of the semiconductor chip 4 respectively so that the inner leads 1 are spaced from the top surface of the "'"'"semiconductor chip 4. The inner leads 1 have stitched portions 2 positioned in inside terminal portions thereof. The stitched portions 2 of the inner leads 1 are positioned outside of the bonding pads. The inner leads 1 extend 2s substantially in parallel to each other and along a direction vertical to the *center line of the semiconductor chip 4. Bonding wires 5 electrically connect the stitched portions 2 of the inner leads 1 to corresponding ones of the bonding pads of the semiconductor chip 4.
First (left) and second (right) side electrically insulative adhesive 3 inner tapes 3A are provided for adhering the semiconductor chip 4 to the stitched portions of the inner leads 1. Each of the electrically insulative adhesive inner tapes 3A has top and bottom surfaces with adhesion force.
For example, it may be possible as illustrated in FIG. 10, that the electrically insulative adhesive inner tape 3A may comprise a sandwich 3 multi-layer structure of a base material layer 9 which has a high flexibility sandwiched between adhesive layers 8. Alternatively, a single layered 0) 0 Page 63 Pf-2090/nec/Australia/mh structure is also available provided that the tape has a sufficient adhesive force. The bottom surfaces of the first and second side electrically insulative adhesive inner tapes 3A are adhered onto first and second inner stripe regions of the semiconductor chip 4 in the process for adhering the semiconductor chip onto the inner leads 1 of a lead frame. The first and second inner stripe regions are positioned outside of the bonding pads. The top surfaces of the first and second side electrically insulative adhesive inner tapes 3A have previously been adhered on bottom surfaces of the stitched portions 2 of the inner leads 1 before the process for adhering the i semiconductor chip onto the inner leads 1 of a lead frame.
For the present invention, it is also important that first and second side electrically insulative adhesive outer tapes 3B are selectively provided which reside in the vicinity of four corners of the semiconductor chip 4 to adhere only outer-most two and second outer two of the inner is leads 1 in the vicinity of the edges of the semiconductor chip 4. An outside edge of each of the first and second side electrically insulative adhesive outer tapes 3B is positioned slightly inside of the edge of the semiconductor chip 4, so that the outer-most two and second outer two of the inner leads 1 are fixed not only in the stitched portions 2 but also outer S 2o positions in the vicinity of the edge of the semiconductor chip 4.
n accordance with the present invention, the semiconductor chip 4 and the inner leads 1 aligned are fixed by the electrically insulative adhesive tapes at a plurality of positions which are distanced from each other to keep a positional balance of fixing points so as to certainly prevent S2- the any substantive movement of the semiconductor chip 4 particularly in the'direction vertical to the surface of the semiconductor chip 4.
Namely, the presence of the electrically insulative adhesive outer tapes 3B would result in that the outer-most two and second outer two of 0oeo the inner leads 1 are fixed not only at the stitched portions 2 but also outside portions in the vicinity of the edges of the semiconductor chip 4.
This structure is capable of certainly preventing a substantive movement of the semiconductor chip 4 in a direction vertical to the surface of the semiconductor chip 4 by pressure of the flow of the molten resin when the resin is injected into dies for packaging the semiconductor chip 4. The 3- certain prevention of the substantive movement of the semiconductor chip 4 would result in a certain prevention of the inner leads 1 from being made Page 64 Pf-2090/nec/Australia/mh into contact with the edges of the semiconductor chip 4. The certain prevention of the substantive movement of the semiconductor chip 4 would also result in a certain prevention of the top portion of the semiconductor device such as tops of bonding wires from exposure from the sealing resin s or a package 6. The certain prevention of the substantive movement of the semiconductor chip 4 would also result in a certain prevention of the bottom portion of the semiconductor device such as the bottom surface of the semiconductor chip 4 from exposure from the sealing resin or the package 6. The certain prevention of the substantive movement of the to semiconductor chip 4 means that the above structure is also capable of keeping a constant distance between the semiconductor chip 4 and the inner lead 1 extending over the semiconductor chip 4. The certain prevention of the substantive movement of the semiconductor chip 4 also means that the structure is capable of keeping a balance in thickness between upper and I- lower portions of the sealing resin 6 for packaging the semiconductor chip 4 due to no substantive movement nor shift in the direction vertical to the surface of the semiconductor chip 4. Keeping the balance in thickness between upper and lower portions of the sealing resin 6 prevents formation of. any thickness-reduced portion of the sealing resin 6, resulting in a ~2o remarkable reduction in the probability in appearance of crack on the thickness-reduced portion of the resin 6. From the above description, it can understood that the above novel structure allows a high yield of manufacturing the semiconductor device and also allows the semiconductor device to have a high reliability.
EIGHTH EMBODIMENT: An eighth embodiment according to the present invention will be described in detail with reference to FIGS. 26 and 10, wherein a novel leadon-chip structure of a semiconductor is provided. FIG. 26 is a fragmentary plane view illustrative of a novel lead-on-chip structure of a semiconductor device.
The lead-on-chip structure comprises the following elements. A semiconductor chip 4 has a top surface which further has two alignments of bonding pads along opposite sides of a center line of the semiconductor chip 4. The center line separates the semiconductor chip 4 into first (left) ?s and second (right) side regions. First and second alignments of inner leads Page Pf-2090/nec/Australia/mh 1 extend over the first and second side regions of the semiconductor chip 4 respectively so that the inner leads 1 are spaced from the top surface of the semiconductor chip 4. The inner leads 1 have stitched portions 2 positioned in inside terminal portions thereof. The stitched portions 2 of the inner leads 1 are positioned outside of the bonding pads. The inner leads 1 extend substantially in parallel to each other and along a direction vertical to the center line of the semiconductor chip 4. Bonding wires 5 electrically connect the stitched portions 2 of the inner leads 1 to corresponding ones of the bonding pads of the semiconductor chip 4.
,o First (left) and second (right) side electrically insulative adhesive inner tapes 3A are provided for adhering the semiconductor chip 4 to the stitched portions of the inner leads 1. Each of the electrically insulative adhesive inner tapes 3A has top and bottom surfaces with adhesion force.
For example, it may be possible as illustrated in FIG. 10, that the electrically insulative adhesive inner tape 3A may comprise a sandwich multi-layer structure of a base material layer 9 which has a high flexibility sandwiched between adhesive layers 8. Alternatively, a single layered structure is also available provided that the tape has a sufficient adhesive force. The bottom surfaces of the first and second side electrically 2i 0 2 insulative adhesive inner tapes 3A are adhered onto first and second inner stripe regions of the semiconductor chip 4 in the process for adhering the semiconductor chip onto the inner leads 1 of a lead frame. The first and second inner stripe regions are positioned outside of the bonding pads. The top surfaces of the first and second side electrically insulative adhesive 2s inner tapes 3A have previously been adhered on bottom surfaces of the ooo stitched portions 2 of the inner leads 1 before the process for adhering the semiconductor chip onto the inner leads 1 of a lead frame.
For the present invention, it is also important that first and seCond side electrically insulative adhesive outer tapes 3B are selectively o provided which reside in the vicinity of four corners of the semiconductor 0"chip 4 to adhere only outer-most two of the inner leads 1 in the vicinity of the edges of the semiconductor chip 4. An outside edge of each of the first and second side electrically insulative adhesive outer tapes 3B is positioned slightly inside of the edge of the semiconductor chip 4, so that the outermost two of the inner leads 1 are fixed not only in the stitched portions 2 but also outer positions in the vicinity of the edge of the semiconductor Page 66 Pf-2090/nec/Australia/mh chip 4.
Further, the outer-most two of the inner leads 1 have spread portions 7 which are adhered with the electrically insulative adhesive outer tapes 3B, so as to increase an adhering area between the inner leads 1 and the electrically insulative adhesive outer tapes 3B and decrease a contact area between the electrically insulative adhesive outer tapes 3b with the sealing resin material 6 for packaging the semiconductor chip 4. If an adhesion force of the electrically insulative adhesive tapes 3A and 3B with the sealing resin 6 is relatively weak, it is particularly effective to reduce to the contact area between the electrically insulative adhesive tapes 3A and 3B and the sealing resin 6 for obtaining a high fixing force between the semiconductor chip 4 and the sealing resin 6.
In accordance with the present invention, the semiconductor chip 4 and the inner leads 1 aligned are fixed by the electrically insulative ts- adhesive tapes at a plurality of positions which are distanced from each other to keep a positional balance of fixing points so as to certainly prevent the any substantive movement of the semiconductor chip 4 particularly in the direction vertical to the surface of the semiconductor chip 4.
Namely, the presence of the electrically insulative adhesive outer 2i o tapes 3B would result in that the outer-most two of the inner leads 1 are io fixed not only at the stitched portions 2 but also outside portions in the ooevicinity of the edges of the semiconductor chip 4. This structure is capable of certainly preventing a substantive movement of the semiconductor chip 4 in a direction vertical to the surface of the semiconductor chip 4 by 2 3- pressure of the flow of the molten resin when the resin is injected into dies for packaging the semiconductor chip 4. The certain prevention of the substantive movement of the semiconductor chip 4 would result in a certain prevention of the inner leads 1 from being made into contact with the edges of the semiconductor chip 4. The certain prevention of the substantive 3o movement of the semiconductor chip 4 would also result in a certain oo S.•"prevention of the top portion of the semiconductor device such as tops of bonding wires from exposure from the sealing resin or a package 6. The certain prevention of the substantive movement of the semiconductor chip 4 would also result in a certain prevention of the bottom portion of the 3s- semiconductor device such as the bottom surface of the semiconductor chip 4 from exposure from the sealing resin or the package 6. The certain Page 67 Pf-2090/nec/Australia/mh prevention of the substantive movement of the semiconductor chip 4 means that the above structure is also capable of keeping a constant distance between the semiconductor chip 4 and the inner lead 1 extending over the semiconductor chip 4. The certain prevention of the substantive movement Sof the semiconductor chip 4 also means that the structure is capable of keeping a balance in thickness between upper and lower portions of the sealing resin 6 for packaging the semiconductor chip 4 due to no substantive movement nor shift in the direction vertical to the surface of the semiconductor chip 4. Keeping the balance in thickness between upper and '0 lower portions of the sealing resin 6 prevents formation of any thicknessreduced portion of the sealing resin 6, resulting in a remarkable reduction in the probability in appearance of crack on the thickness-reduced portion of the resin 6. From the above description, it can be understood that the above novel structure allows a high yield of manufacturing the semiconductor device and also allows the semiconductor device to have a high reliability.
NINTH EMBODIMENT A ninth embodiment according to the present invention will be _o described in detail with reference to FIG. 21 and 10, wherein a novel leadi"'o o on-chip structure of a semiconductor is provided. FIG. 21 is a fragmentary :°oooplane view illustrative of a novel lead-on-chip structure of a semiconductor :device.
The lead-on-chip structure comprises the following elements. A semiconductor chip 4 has a top surface which further has two alignments of 2- bonding pads along opposite sides of a center line of the semiconductor chip 4. The center line separates the semiconductor chip 4 into first (left) and second (right) side regions. First and second alignments of inner leads 1 extend over the first and second side regions of the semiconductor chip 4 respectively so that the inner leads 1 are spaced from the top surface of the 3o semiconductor chip 4. The inner leads 1 have stitched portions 2 positioned in inside terminal portions thereof. The stitched portions 2 of the inner leads 1 are positioned outside of the bonding pads. The inner leads 1 extend substantially in parallel to each other and along a direction vertical to the center line of the semiconductor chip 4. Bonding wires 5 electrically connect the stitched portions 2 of the inner leads 1 to corresponding ones of Page 68 Pf-2090/nec/Australia/mh the bonding pads of the semiconductor chip 4.
First (left) and second (right) side electrically insulative adhesive inner tapes 3A are provided for adhering the semiconductor chip 4 to the stitched portions of the inner leads 1. Each of the electrically insulative adhesive inner tapes 3A has top and bottom surfaces with adhesion force.
For example, it may be possible as illustrated in FIG. 10, that the electrically insulative adhesive inner tape 3A may comprise a sandwich multi-layer structure of a base material layer 9 which has a high flexibility sandwiched between adhesive layers 8. Alternatively, a single layered ,o structure is also available provided that the tape has a sufficient adhesive force. The bottom surfaces of the first and second side electrically insulative adhesive inner tapes 3A are adhered onto first and second inner stripe regions of the semiconductor chip 4 in the process for adhering the semiconductor chip onto the inner leads 1 of a lead frame. The first and IT second inner stripe regions are positioned outside of the bonding pads. The top surfaces of the first and second side electrically insulative adhesive inner tapes 3A have previously been adhered on bottom surfaces of the stitched portions 2 of the inner leads 1 before the process for adhering the semiconductor chip onto the inner leads 1 of a lead frame.
For the present invention, it is also important that first and i.o second side electrically insulative adhesive outer tapes 3B are selectively oprovided which reside in the vicinity of four corners of the semiconductor chip 4 to adhere only second outer two of the inner leads 1 in the vicinity of the edges of the semiconductor chip 4. An outside edge of each of the first S2s and second side electrically insulative adhesive outer tapes 3B is positioned slightly inside of the edge of the semiconductor chip 4, so that the second outer two of the inner leads 1 are fixed not only in the stitched portions 2 but also outer positions in the vicinity of the edge of the semiconductor chip 4.
Further, the second outer two of the inner leads 1 have spread portions 7 which are adhered with the electrically insulative adhesive outer see tapes 3B, so as to increase an adhering area between the inner leads 1 and the electrically insulative adhesive outer tapes 3B and decrease a contact area between the electrically insulative adhesive outer tapes 3b with the sealing resin material 6 for packaging the semiconductor chip 4. If an adhesion force of the electrically insulative adhesive tapes 3A and 3B with Page 69 Pf-2090/nec/Australia/mh the sealing resin 6 is relatively weak, it is particularly effective to reduce the contact area between the electrically insulative adhesive tapes 3A and 3B and the sealing resin 6 for obtaining a high fixing force between the semiconductor chip 4 and the sealing resin 6.
SIn accordance with the present invention, the semiconductor chip 4 and the inner leads 1 aligned are fixed by the electrically insulative adhesive tapes at a plurality of positions which are distanced from each other to keep a positional balance of fixing points so as to certainly prevent the any substantive movement of the semiconductor chip 4 particularly in to the direction vertical to the surface of the semiconductor chip 4.
Namely, the presence of the electrically insulative adhesive outer tapes 3B would result in that the second outer two of the inner leads 1 are fixed not only at the stitched portions 2 but also outside portions in the vicinity of the edges of the semiconductor chip 4. This structure is capable Is of certainly preventing a substantive movement of the semiconductor chip 4 in a direction vertical to the surface of the semiconductor chip 4 by pressure of the flow of the molten resin when the resin is injected into dies for. packaging the semiconductor chip 4. The certain prevention of the substantive movement of the semiconductor chip 4 would result in a certain 2o prevention of the inner leads 1 from being made into contact with the edges of the semiconductor chip 4. The certain prevention of the substantive :oo ~movement of the semiconductor chip 4 would also result in a certain prevention of the top portion of the semiconductor device such as tops of bonding wires from exposure from the sealing resin or a package 6. The °ooo 2- certain prevention of the substantive movement of the semiconductor chip *go* *4 would also result in a certain prevention of the bottom portion of the semiconductor device such as the bottom surface of the semiconductor chip 0. 4 from exposure from the sealing resin or the package 6. The certain prevention of the substantive movement of the semiconductor chip 4 means go that the above structure is also capable of keeping a constant distance between the semiconductor chip 4 and the inner lead 1 extending over the semiconductor chip 4. The certain prevention of the substantive movement of the semiconductor chip 4 also means that the structure is capable of keeping a balance in thickness between upper and lower portions of the 36- sealing resin 6 for packaging the semiconductor chip 4 due to no substantive movement nor shift in the direction vertical to the surface of the Page Pf-2090/nec/Australia/mh semiconductor chip 4. Keeping the balance in thickness between upper and lower portions of the sealing resin 6 prevents formation of any thicknessreduced portion of the sealing resin 6, resulting in a remarkable reduction in the probability in appearance of crack on the thickness-reduced portion s of the resin 6. From the above description, it can be understood that the above novel structure allows a high yield of manufacturing the semiconductor device and also allows the semiconductor device to have a high reliability.
TENTH EMBODIMENT A tenth embodiment according to the present invention will be described in detail with reference to FIGS. 28 and 10, wherein a novel leadon-chip structure of a semiconductor is provided. FIG. 28 is a fragmentary plane view illustrative of a novel lead-on-chip structure of a semiconductor device.
16 The lead-on-chip structure comprises the following elements. A semiconductor chip 4 has a top surface which further has two alignments of bonding pads along opposite sides of a center line of the semiconductor chip 4. The center line separates the semiconductor chip 4 into first (left) i" .and second (right) side regions. First and second alignments of inner leads 2o 1 extend over the first and second side regions of the semiconductor chip 4 "°'"respectively so that the inner leads 1 are spaced from the top surface of the semiconductor chip 4. The inner leads 1 have stitched portions 2 positioned in inside terminal portions thereof. The stitched portions 2 of the inner leads 1 are positioned outside of the bonding pads. The inner leads 1 extend 2s5 substantially in parallel to each other and along a direction vertical to the center line of the semiconductor chip 4. Bonding wires 5 electrically connect the stitched portions 2 of the inner leads 1 to corresponding ones of the bonding pads of the semiconductor chip 4.
First (left) and second (right) side electrically insulative adhesive o inner tapes 3A are provided for adhering the semiconductor chip 4 to the stitched portions of the inner leads 1. Each of the electrically insulative adhesive inner tapes 3A has top and bottom surfaces with adhesion force.
For example, it may be possible as illustrated in FIG. 10, that the electrically insulative adhesive inner tape 3A may comprise a sandwich 356- multi-layer structure of a base material layer 9 which has a high flexibility Page 71 Pf-2090/nec/Australia/mh sandwiched between adhesive layers 8. Alternatively, a single layered structure is also available provided that the tape has a sufficient adhesive force. The bottom surfaces of the first and second side electrically insulative adhesive inner tapes 3A are adhered onto first and second inner stripe regions of the semiconductor chip 4 in the process for adhering the semiconductor chip onto the inner leads 1 of a lead frame. The first and second inner stripe regions are positioned outside of the bonding pads. The top surfaces of the first and second side electrically insulative adhesive inner tapes 3A have previously been adhered on bottom surfaces of the 1o stitched portions 2 of the inner leads 1 before the process for adhering the semiconductor chip onto the inner leads 1 of a lead frame.
For the present invention, it is also important that first and second side electrically insulative adhesive outer tapes 3B are selectively provided which reside in the vicinity of four corners of the semiconductor 1 chip 4 to adhere only outer-most two and second outer two of the inner leads 1 in the vicinity of the edges of the semiconductor chip 4. An outside edge of each of the first and second side electrically insulative adhesive outer tapes 3B is positioned slightly inside of the edge of the semiconductor chip 4, so that the outer-most two and second outer two of .:o 20 the inner leads 1 are fixed not only in the stitched portions 2 but also outer I positions in the vicinity of the edge of the semiconductor chip 4.
:too& Further, the outer-most two and the second outer two of the inner leads 1 have spread portions 7 which are adhered with the electrically insulative adhesive outer tapes 3B, so as to increase an adhering area 2 z5 between the inner leads 1 and the electrically insulative adhesive outer tapes 3B and decrease a contact area between the electrically insulative adhesive outer tapes 3b with the sealing resin material 6 for packaging the semiconductor chip 4. If an adhesion force of the electrically insulative aeaseadhesive tapes 3A and 3B with the sealing resin 6 is relatively weak, it is 3o particularly effective to reduce the contact area between the electrically "°insulative adhesive tapes 3A and 3B and the sealing resin 6 for obtaining a oboehigh fixing force between the semiconductor chip 4 and the sealing resin 6.
In accordance with the present invention, the semiconductor chip 4 and the inner leads 1 aligned are fixed by the electrically insulative 36 adhesive tapes at a plurality of positions which are distanced from each other to keep a positional balance of fixing points so as to certainly prevent Page 72 Pf-2090/nec/Australia/mh the any substantive movement of the semiconductor chip 4 particularly in the direction vertical to the surface of the semiconductor chip 4.
Namely, the presence of the electrically insulative adhesive outer tapes 3B would result in that the outer-most two and second outer two of s- the inner leads 1 are fixed not only at the stitched portions 2 but also outside portions in the vicinity of the edges of the semiconductor chip 4.
This structure is capable of certainly preventing a substantive movement of the semiconductor chip 4 in a direction vertical to the surface of the semiconductor chip 4 by pressure of the flow of the molten resin when the ,o resin is injected into dies for packaging the semiconductor chip 4. The certain prevention of the substantive movement of the semiconductor chip 4 would result in a certain prevention of the inner leads 1 from being made into contact with the edges of the semiconductor chip 4. The certain prevention of the substantive movement of the semiconductor chip 4 would also result in a certain prevention of the top portion of the semiconductor device such as tops of bonding wires from exposure from the sealing resin or a package 6. The certain prevention of the substantive movement of the semiconductor chip 4 would also result in a certain prevention of the bottom portion of the semiconductor device such as the bottom surface of 20 the semiconductor chip 4 from exposure from the sealing resin or the package 6. The certain prevention of the substantive movement of the semiconductor chip 4 means that the above structure is also capable of keeping a constant distance between the semiconductor chip 4 and the inner lead 1 extending over the semiconductor chip 4. The certain prevention of 25 the substantive movement of the semiconductor chip 4 also means that the structure is capable of keeping a balance in thickness between upper and lower portions of the sealing resin 6 for packaging the semiconductor chip 4 due to no substantive movement nor shift in the direction vertical to the surface of the semiconductor chip 4. Keeping the balance in thickness ,30 between upper and lower portions of the sealing resin 6 prevents formation 000.-of any thickness-reduced portion of the sealing resin 6, resulting in a remarkable reduction in the probability in appearance of crack on the thickness-reduced portion of the resin 6. From the above description, it can be. understood that the above novel structure allows a high yield of manufacturing the semiconductor device and also allows the semiconductor device to have a high reliability.
Page 73 Pf-2090/nec/Australia/mh ELEVNTH EMBODIMENT: An eleventh embodiment according to the present invention will be described in detail with reference to FIGS. 29, 30, 31, 32 and wherein a novel lead-on-chip structure of a semiconductor is provided. FIG.
29 is a fragmentary plane view illustrative of a novel lead-on-chip structure of a semiconductor device. FIG. 30 is a fragmentary cross sectional elevation view illustrative of a novel lead-on-chip structure of a semiconductor device. FIG. 31 is a fragmentary cross sectional elevation view illustrative of a novel lead-on-chip structure semiconductor device io packaged with a sealing resin wherein a semiconductor chip had received up-force by a molten resin when the resin was injected into dies in a first embodiment in accordance with the present invention. FIG. 32 is a fragmentary cross sectional elevation view illustrative of a novel lead-onchip structure semiconductor device packaged with a sealing resin wherein is- a semiconductor chip had received down-force by a molten resin when the resin was injected into dies.
The lead-on-chip structure comprises the following elements. A o. semiconductor chip 4 has a top surface which further has two alignments of bonding pads along opposite sides of a center line of the semiconductor 2-o chip 4. The center line separates the semiconductor chip 4 into first (left) and second (right) side regions. First and second alignments of inner leads 1 extend over the first and second side regions of the semiconductor chip 4 respectively so that the inner leads 1 are spaced from the top surface of the semiconductor chip 4. The inner leads 1 have stitched portions 2 positioned 2 s- in inside terminal portions thereof. The stitched portions 2 of the inner *:leads 1 are positioned outside of the bonding pads. The inner leads 1 extend substantially in parallel to each other and along a direction vertical to the center line of the semiconductor chip 4. Bonding wires 5 electrically :connect the stitched portions 2 of the inner leads 1 to corresponding ones of 30 the bonding pads of the semiconductor chip 4.
First (left) and second (right) side electrically insulative adhesive tapes 3C are provided for adhering the semiconductor chip 4 to the stitched portions of the inner leads 1. Each of the electrically insulative adhesive tapes 3C has top and bottom surfaces with adhesion force. For example, it may be possible as illustrated in FIG. 10, that the electrically insulative Page 74 Pf-2090/nec/Australia/mh adhesive inner tape 3C may comprise a sandwich multi-layer structure of a base material layer 9 which has a high flexibility sandwiched between adhesive layers 8. Alternatively, a single layered structure is also available provided that the tape has a sufficient adhesive force. The bottom surfaces s of the first and second side electrically insulative adhesive tapes 3C are adhered almost entirely onto first and second regions of the semiconductor chip 4 in the process for adhering the semiconductor chip onto the inner leads 1 of a lead frame. The top surfaces of the first and second side electrically insulative adhesive tapes 3B have previously been adhered on to bottom surfaces of the inner leads 1 extending over the semiconductor chip 4 before the process for adhering the semiconductor chip 4 onto the inner leads 1 of a lead frame. The first and second side electrically insulative adhesive tapes 3C extend from the inside portions up to opposite edges of the semiconductor chip 4 so that an outside edge of each of the first and second side electrically insulative adhesive tapes 3c is positioned in correspondence to the edge of the semiconductor chip 4, whereby the inner leads 1 are fixed in the entire portions extending over the semiconductor chip 4.
In accordance with the present invention, the semiconductor chip 2o 4 and the inner leads 1 aligned are fixed by the electrically insulative adhesive tapes at entire positions to keep a positional balance of fixing *points so as to certainly prevent the any substantive movement of the semiconductor chip 4 particularly in the direction vertical to the surface of the semiconductor chip 4.
Namely, the presence of the electrically insulative adhesive tapes 3C would result in that inner leads 1 are fixed not only at the stitched *:portions 2 but also any other portions extending over the semiconductor chip 4. This structure is capable of certainly preventing a substantive movement of the semiconductor chip 4 in a direction vertical to the surface 30 of the semiconductor chip 4 by pressure of the flow of the molten resin when the resin is injected into dies for packaging the semiconductor chip 4.
The certain prevention of the substantive movement of the semiconductor chip 4 would result in a certain prevention of the inner leads 1 from being made into contact with the edges of the semiconductor chip 4. The certain gs prevention of the substantive movement of the semiconductor chip 4 would also result in a certain prevention of the top portion of the semiconductor Page Pf-2090/nec/Australia/mh device such as tops of bonding wires from exposure from the sealing resin or a package 6. The certain prevention of the substantive movement of the semiconductor chip 4 would also result in a certain prevention of the bottom portion of the semiconductor device such as the bottom surface of the semiconductor chip 4 from exposure from the sealing resin or the package 6. The certain prevention of the substantive movement of the semiconductor chip 4 means that the above structure is also capable of keeping a constant distance between the semiconductor chip 4 and the inner lead 1 extending over the semiconductor chip 4. The certain prevention of I 0 the substantive movement of the semiconductor chip 4 also means that the structure is capable of keeping a balance in thickness between upper and lower portions of the sealing resin 6 for packaging the semiconductor chip 4 due to no substantive movement nor shift in the direction vertical to the surface of the semiconductor chip 4. Keeping the balance in thickness Is between upper and lower portions of the sealing resin 6 prevents formation of any thickness-reduced portion of the sealing resin 6, resulting in a remarkable reduction in the probability in appearance of crack on the thickness-reduced portion of the resin 6. From the above description, it can be understood that the above novel structure allows a high yield of 20 manufacturing the semiconductor device and also allows the semiconductor device to have a high reliability.
TWELFTH EMBODIMENT: A twelfth embodiment according to the present invention will be described in detail with reference to FIGS. 33 and 10, wherein a novel leadon-chip structure of a semiconductor is provided. FIG. 33 is a fragmentary plane view illustrative of a novel chip-on-lead structure of a semiconductor Sdevice.
The chip-on-lead structure comprises the following elements. A :semiconductor chip 4 has a top surface which further has two alignments of 3o bonding pads along opposite side edges of the semiconductor chip 4. A center line separates the semiconductor chip 4 into first (left) and second (right) side regions. First and second alignments of inner leads 1 extend under the first and second side regions of the semiconductor chip 4 respectively so that the inner leads 1 are spaced from the bottom surface of 3- the semiconductor chip 4. The inner leads 1 have stitched portions 2 Page 76 Pf-2090/nec/Australia/mh positioned in inside terminal portions thereof. The inner leads 1 extend substantially in parallel to each other and along a direction vertical to the center line of the semiconductor chip 4. Bonding wires 5 electrically connect the outer portions of the inner leads 1 to corresponding ones of the pads of the semiconductor chip 4.
First (left) and second (right) side electrically insulative adhesive inner tapes 3A are provided for adhering the semiconductor chip 4 to the stitched portions of the inner leads 1. Each of the electrically insulative adhesive inner tapes 3A has top and bottom surfaces with adhesion force.
to For example, it may be possible as illustrated in FIG. 10, that the electrically insulative adhesive inner tape 3A may comprise a sandwich multi-layer structure of a base material layer 9 which has a high flexibility sandwiched between adhesive layers 8. Alternatively, a single layered structure is also available provided that the tape has a sufficient adhesive ri force. The top surfaces of the first and second side electrically insulative adhesive inner tapes 3A are adhered onto first and second inner stripe regions of the semiconductor chip 4 in the process for adhering the semiconductor chip onto the inner leads 1 of a lead frame. The bottom surfaces of the first and second side electrically insulative adhesive inner tapes 3A have previously been adhered on top surfaces of the stitched portions 2 of the inner leads 1 before the process for adhering the semiconductor chip onto the inner leads 1 of a lead frame.
For the present invention, it is also important that first and second side electrically insulative adhesive outer tapes 3B are further 25 provided which extend on outer stripe regions in the vicinity of and in parallel to opposite edges of the semiconductor chip 4, where the outer .:.:.stripe regions are separated from the inner stripe regions. An outside edge of each of the first and second side electrically insulative adhesive outer tapes 3B is positioned in correspondence to the edge of the semiconductor 3o chip 4, so that the inner leads 1 are fixed not only in the stitched portions 2 but also outer positions at the edge of the semiconductor chip 4.
In accordance with the present invention, the semiconductor chip 4 and the inner leads 1 aligned are fixed by the electrically insulative adhesive tapes at a plurality of positions which are distanced from each ?S other to keep a positional balance of fixing points so as to certainly prevent the any substantive movement of the semiconductor chip 4 particularly in Page 77 p. r Pf-2090/nec/Australia/mh the direction vertical to the surface of the semiconductor chip 4.
Namely, the presence of the electrically insulative adhesive outer tapes 3B would result in that inner leads 1 are fixed not only at the stitched portions 2 but also outside portions at the edges of the semiconductor chip 4. This structure is capable of certainly preventing a substantive movement of the semiconductor chip 4 in a direction vertical to the surface of the semiconductor chip 4 by pressure of the flow of the molten resin when the resin is injected into dies for packaging the semiconductor chip 4. The certain prevention of the substantive movement of the semiconductor chip o 4 would result in a certain prevention of the inner leads 1 from being made into contact with the edges of the semiconductor chip 4. The certain prevention of the substantive movement of the semiconductor chip 4 would also result in a certain prevention of the top portion of the semiconductor device such as tops of bonding wires from exposure from the sealing resin or a package 6. The certain prevention of the substantive movement of the semiconductor chip 4 would also result in a certain prevention of the bottom portion of the semiconductor device such as the bottom surface of the inner leads 1 from exposure from the sealing resin or the package 6.
The certain prevention of the substantive movement of the semiconductor o chip 4 means that the above structure is also capable of keeping a constant distance between the semiconductor chip 4 and the inner lead 1 extending over the semiconductor chip 4. The certain prevention of the substantive movement of the semiconductor chip 4 also means that the structure is capable of keeping a balance in thickness between upper and lower 2s- portions of the sealing resin 6 for packaging the semiconductor chip 4 due to no substantive movement nor shift in the direction vertical to the surface S.0. of the semiconductor chip 4. Keeping the balance in thickness between upper and lower portions of the sealing resin 6 prevents formation of any thickness-reduced portion of the sealing resin 6, resulting in a remarkable z3c reduction in the probability in appearance of crack on the thickness- "000 reduced portion of the resin 6. From the above description, it can be understood that the above novel structure allows a high yield of manufacturing the semiconductor device and also allows the semiconductor device to have a high reliability.
31 Whereas modifications of the present invention will be apparent to a person having ordinary skill in the art, to which the invention pertains, Page 78 Pf-2090/nec/Australia/mh it is to be understood that embodiments as shown and described by way of illustrations are by no means intended to be considered in a limiting sense.
Accordingly, it is to be intended to cover by claims all modifications which fall within the spirit and scope of the present invention.
0 5o Page 79

Claims (45)

1. An adhering structure between a semiconductor chip and two alignments of first side inner leads and second side inner leads extending in first and second sides of said semiconductor chip respectively, each of said first and second side inner leads having a stitched portion, said first and second sides being separated by a center line of said semiconductor chip, said semiconductor chip and said first and second side inner leads being adhered to each other by first and second side electrically insulative adhesive tapes respectively, each of said first and second side electrically insulative adhesive tapes having both surfaces with adhesion force, said first and second side electrically insulative adhesive tapes extending on first and second inner stripe regions so as to adhere said stitched portions of said first and second side inner leads respectively, wherein each of said first and second side electrically insulative adhesive tapes is further present in at least two positions which are spaced from each other in a direction parallel to said center line and which are also located in the vicinity of an edge of said semiconductor chip, where said edge extends substantially in parallel to said center line, so that said inner leads, which extend through said two positions, are also fixed in the 2o vicinity of said edge of said semiconductor chip.
2. The adhering structure as claimed in claim 1, wherein each of said first and second side electrically insulative adhesive tapes is further positioned so as to adhere outer-most two of said inner leads.
3. The adhering structure as claimed in claim 2, wherein said outer- 2s most two of said inner leads have spread portions which are adhered with said electrically insulative adhesive tape, so as to increase an adhering area between said inner leads and said electrically insulative adhesive tape and decrease a contact area between said electrically insulative adhesive tape with a sealing resin material for packaging said semiconductor chip. 3o
4. The adhering structure as claimed in claim 1, wherein each of said first and second side electrically insulative adhesive tapes is further positioned so as to adhere secondly outer two of said inner leads.
Page Pf-2090/nec/Australia/mh The adhering structure as claimed in claim 4, wherein said secondly outer two of said inner leads have spread portions which are adhered with said electrically insulative adhesive tape, so as to increase an adhering, area between said inner leads and said electrically insulative Sadhesive tape and decrease a contact area between said electrically insulative adhesive tape with a sealing resin material for packaging said semiconductor chip.
6. The adhering structure as claimed in claim 1, wherein each of said first and second side electrically insulative adhesive tapes is further ,o positioned so as to adhere outer-most two and secondly outer two of said inner leads.
7. The adhering structure as claimed in claim 6, wherein said outer- most two and said secondly outer two of said inner leads have spread portions which are adhered with said electrically insulative adhesive tape, s so as to increase an adhering area between said inner leads and said electrically insulative adhesive tape and decrease a contact area between said electrically insulative adhesive tape with a sealing resin material for packaging said semiconductor chip. 0
8. The adhering structure as claimed in claim 1, wherein each of 2 o said first and second side electrically insulative adhesive tapes is further positioned so as to adhere outer-most one of said inner leads and secondly outer .one in an opposite side to said outer-most one.
9. The adhering structure as claimed in claim 8, wherein said outer- most one of said inner leads and said secondly outer one in an opposite side z257 to said outer-most one of said inner leads have spread portions which are 00 .adhered with said electrically insulative adhesive tape, so as to increase an adhering area between said inner leads and said electrically insulative adhesive tape and decrease a contact area between said electrically insulative adhesive tape with a sealing resin material for packaging said 0so semiconductor chip.
Page 81 Pf-2090/nec/Australia/mh The adhering structure as claimed in claim 1, wherein each of said first and second side electrically insulative adhesive tapes further extends on an outer stripe region in the vicinity of and in parallel to said edge of said semiconductor chip, where said outer stripe region is separated from said inner stripe region, and an outside edge of said each of said first and second side electrically insulative adhesive tapes is positioned inside of said edge of said semiconductor chip.
11. The adhering structure as claimed in claim 10, wherein said inner leads have spread portions which are adhered with said electrically ,t insulative adhesive tape, provided that said spread portions of said adjacent two of said inner leads are separated from each other, so as to increase an adhering area between said inner leads and said electrically insulative adhesive tape and decrease a contact area between said electrically insulative adhesive tape with a sealing resin material for packaging said is semiconductor chip.
12. The adhering structure as claimed in claim 1, wherein each of said first and second side electrically insulative adhesive tapes further extends on an outer stripe region along said edge of said semiconductor chip, where said outer stripe region is separated from said inner stripe to region, and an outside edge of said each of said first and second side electrically insulative adhesive tapes is positioned in correspondence to said edge of said semiconductor chip.
13. The adhering structure as claimed in claim 12, wherein said inner leads have spread portions which are adhered with said electrically *2zs- insulative adhesive tape, provided that said spread portions of said adjacent two of said inner leads are separated from each other, so as to increase an adhering area between said inner leads and said electrically insulative adhesive tape and decrease a contact area between said electrically insulative adhesive tape with a sealing resin material for packaging said semiconductor chip.
14. The adhering structure as claimed in claim 1, wherein each of said first and second side electrically insulative adhesive tapes continuously Page 82 Pf-2090/nec/Australia/mh extends from said inner stripe region to said outer stripe region in the vicinity of and in parallel to said edge of said semiconductor chip so that an outside edge of said each of said first and second side electrically insulative adhesive tapes is positioned inside of said edge of said semiconductor chip. s
15. The adhering structure as claimed in claim 1, wherein each of said first and second side electrically insulative adhesive tapes continuously extends from said inner stripe region through said edge of said semiconductor chip so that an outside edge of said each of said first and second side electrically insulative adhesive tapes is positioned in ,o correspondence to said edge of said semiconductor chip.
16. An electrically insulative adhesive tape structure to be used for adhering a semiconductor chip with inner leads extending substantially in parallel to each other and being aligned in a direction substantially in parallel to an edge of said semiconductor chip, each of said inner leads IS having an inside portion, said semiconductor chip and said inner leads being adhered to each other by said electrically insulative adhesive tape, said electrically insulative adhesive tape having both surfaces with adhesion force, said electrically insulative adhesive tape extending on an inner stripe region so as to adhere said inside portions of said inner leads, *e wherein said electrically insulative adhesive tape is further present in at least two positions which are spaced from each other in a direction parallel to said edge of said semiconductor chip and which are also located in the vicinity of said edge of said semiconductor chip so that said inner leads, which extend through said two positions, are also adhered y- 5 in the vicinity of said edge of said semiconductor chip.
17. The electrically insulative adhesive tape structure as claimed in claim 16, wherein said electrically insulative adhesive tape is further positioned so as to adhere outer-most two of said inner leads.
18. The electrically insulative adhesive tape structure as claimed in claim 17, wherein said outer-most two of said inner leads have spread portions which are adhered with said electrically insulative adhesive tape, so as to increase an adhering area between said inner leads and said Page 83 Pf-2090/nec/Australialmh electrically insulative adhesive tape and decrease a contact area between said electrically insulative adhesive tape with a sealing resin material for packaging said semiconductor chip.
19. The electrically insulative adhesive tape structure as claimed in a- claim 16, wherein said electrically insulative adhesive tape is further positioned so as to adhere secondly outer two of said inner leads.
The electrically insulative adhesive tape structure as claimed in claim 19, wherein said secondly outer two of said inner leads have spread portions which are adhered with said electrically insulative adhesive tape, o( so as to increase an adhering area between said inner leads and said electrically insulative adhesive tape and decrease a contact area between said electrically insulative adhesive tape with a sealing resin material for packaging said semiconductor chip.
21. The electrically insulative adhesive tape structure as claimed in 1 claim 20, wherein said electrically insulative adhesive tape is further positioned so as to adhere outer-most two and secondly outer two of said inner leads.
22. The electrically insulative adhesive tape structure as claimed in claim 21, wherein said outer-most two and said secondly outer two of said 2~ inner leads have spread portions which are adhered with said electrically insulative adhesive tape, so as to increase an adhering area between said inner leads and said electrically insulative adhesive tape and decrease a contact area between said electrically insulative adhesive tape with a sealing resin material for packaging said semiconductor chip. z i
23. The electrically insulative adhesive tape structure as claimed in claim 16, wherein said electrically insulative adhesive tape is further positioned so as to adhere outer-most one of said inner leads and secondly outer one in an opposite side to said outer-most one.
24. The electrically insulative adhesive tape structure as claimed in so claim 23, wherein said outer-most one of said inner leads and said secondly Page 84 Pf-2090/nec/Australia/mh outer one in an opposite side to said outer-most one of said inner leads have spread portions which are adhered with said electrically insulative adhesive tape, so as to increase an adhering area between said inner leads and said electrically insulative adhesive tape and decrease a contact area between s said electrically insulative adhesive tape with a sealing resin material for packaging said semiconductor chip.
The electrically insulative adhesive tape structure as claimed in claim 16, wherein said electrically insulative adhesive tapes further extend on an outer stripe region in the vicinity of and in parallel to said edge of to said semiconductor chip, where said outer stripe region is separated from said inner stripe region, and an outside edge of said electrically insulative adhesive tape is positioned inside of said edge of said semiconductor chip.
26. The electrically insulative adhesive tape structure as claimed in claim 25, wherein said inner leads have spread portions which are adhered is with said electrically insulative adhesive tape, provided that said spread portions of said adjacent two of said inner leads are separated from each other, so as to increase an adhering area between said inner leads and said electrically insulative adhesive tape and decrease a contact area between said electrically insulative adhesive tape with a sealing resin material for 20 packaging said semiconductor chip.
27. The electrically insulative adhesive tape structure as claimed in claim 16, wherein said electrically insulative adhesive tape further extends on an outer stripe region along said edge of said semiconductor chip, where :said outer stripe region is separated from said inner stripe region, and an 2s outside edge of said electrically insulative adhesive tape is positioned in correspondence to said edge of said semiconductor chip. o* 00'
28. The electrically insulative adhesive tape structure as claimed in claim 27, wherein said inner leads have spread portions which are adhered with said electrically insulative adhesive tape, provided that said spread o portions of said adjacent two of said inner leads are separated from each other, so as to increase an adhering area between said inner leads and said electrically insulative adhesive tape and decrease a contact area between Page Pf-2090/nec/Australia/mh said electrically insulative adhesive tape with a sealing resin material for packaging said semiconductor chip.
29. The, electrically insulative adhesive tape structure as claimed in claim 16, wherein said electrically insulative adhesive tape continuously extends from said inner stripe region to said outer stripe region in the vicinity of and in parallel to said edge of said semiconductor chip so that an outside edge of said electrically insulative adhesive tape is positioned inside of said edge of said semiconductor chip.
The electrically insulative adhesive tape structure as claimed in ,o claim 16, wherein said electrically insulative adhesive tape continuously extends from said inner stripe region through said edge of said semiconductor chip so that an outside edge of said electrically insulative adhesive tape is positioned in correspondence to said edge of said semiconductor chip. f's
31. An electrically insulative adhesive tape extending over stitched portions of inner leads of a lead frame, said inner leads extending substantially in parallel to each other and being aligned in a direction substantially vertical to a longitudinal direction of said inner leads, so that said electrically insulative adhesive tape extends on an inner stripe region 2 z over said inner leads so as to adhere said stitched portions of said inner a Page 86 Pf-2090/nec/Australia/mh leads, and said electrically insulative adhesive tape having both surfaces with adhesion force, wherein said electrically insulative adhesive tape is further present in at least two positions which are spaced from each other in a direction vertical to said longitudinal direction of said inner leads and which are also located outside of said stitched portions of said inner leads and said two positions are located in the vicinity of chip edge correspondence positions of said inner leads, where said chip edge correspondence position is previously determined to correspond to an edge o1 of said semiconductor chip after said semiconductor chip has been adhered to'said lead frame by said first and second electrically insulative adhesive tapes.
32. The electrically insulative adhesive tape as claimed in claim 31, wherein said electrically insulative adhesive tape is further positioned so as to adhere outer-most two of said inner leads.
33. The electrically insulative adhesive tape as claimed in claim 32, wherein said outer-most two of said inner leads have spread portions which are.adhered with said electrically insulative adhesive tape, so as to increase an adhering area between said inner leads and said electrically insulative 2-o adhesive tape and decrease an exposed area of said electrically insulative adhesive tape.
34. The electrically insulative adhesive tape as claimed in claim 31, wherein said electrically insulative adhesive tape is further positioned so as to adhere secondly outer two of said inner leads. zr
35. The electrically insulative adhesive tape as claimed in claim 34, wherein said secondly outer two of said inner leads have spread portions which are adhered with said electrically insulative adhesive tape, so as to increase an adhering area between said inner leads and said electrically insulative adhesive tape and decrease an exposed area of said electrically so insulative adhesive tape.
36. The electrically insulative adhesive tape as claimed in claim 31, Page 87 Pf- 2 0 9 0/nec/Australia/mh wherein said electrically insulative adhesive tapes is further positioned so as to adhere outer-most two and secondly outer two of said inner leads.
37. The electrically insulative adhesive tape as claimed in claim 36, wherein said outer-most two and said secondly outer two of said inner s leads have spread portions which are adhered with said electrically insulative adhesive tape, so as to increase an adhering area between said inner leads and said electrically insulative adhesive tape and decrease an exposed area of said electrically insulative adhesive tape.
38. The electrically insulative adhesive tape as claimed in claim 31, 1o wherein said electrically insulative adhesive tape is further positioned so as to adhere outer-most one of said inner leads and secondly outer one in an opposite side to said outer-most one.
39 The electrically insulative adhesive tape as claimed in claim 38, wherein said outer-most one of said inner leads and said secondly outer one in an opposite side to said outer-most one of said inner leads have spread Sportions which are adhered with said electrically insulative adhesive tape, so.as to increase an adhering area between said inner leads and said electrically insulative adhesive tape and decrease an exposed area of said .oelectrically insulative adhesive tape.
40. The electrically insulative adhesive tape as claimed in claim 31, wherein said electrically insulative adhesive tape further extends on an outer stripe region over said inner leads in the vicinity of said chip edge correspondence positions, where said outer stripe region is positioned a outside of and separated from said stitched portion, and an outside edge of 2s said each of said first and second side electrically insulative adhesive tapes is positioned inside of said chip edge correspondence position. 0•
41. The electrically insulative adhesive tape as claimed in claim wherein said inner leads have spread portions which are adhered with said electrically insulative adhesive tape, provided that said spread portions of said adjacent two of said inner leads are separated from each other, so as to increase an adhering area between said inner leads and said electrically Page 88 Pf-2090/nec/Australia/mh insulative adhesive tape and decrease an exposed area of said electrically insulative adhesive tape.
42. The electrically insulative adhesive tape as claimed in claim 31, wherein said electrically insulative adhesive tape further extends on an s- outer stripe region over said inner leads in the vicinity of said chip edge correspondence positions, where said outer stripe region is positioned outside of and separated from said stitched portion, and an outside edge of said electrically insulative adhesive tape is positioned at said chip edge correspondence position. S0
43. The electrically insulative adhesive tape as claimed in claim 42, wherein said inner leads have spread portions which are adhered with said electrically insulative adhesive tape, provided that said spread portions of said adjacent two of said inner leads are separated from each other, so as to increase an adhering area between said inner leads and said electrically r6 insulative adhesive tape and decrease an exposed area of said electrically insulative adhesive tape.
44- The electrically insulative adhesive tape as claimed in claim 31, wherein said electrically insulative adhesive tape continuously extends from said stitched portions to an outer stripe region over said inner leads, z 2 and said outer stripe region is positioned in the vicinity of said chip edge correspondence position so that an outside edge of said electrically insulative adhesive tape is positioned inside of said chip edge correspondence position. 00 0*.
045. The electrically insulative adhesive tape as claimed in claim 31, zs wherein said electrically insulative adhesive tape continuously extends 0. from said stitched portions to said chip edge correspondence position so that an outside edge of said electrically insulative adhesive tape is *0 0 positioned at said chip edge correspondence position. DATED this Thirtieth Day of July, 2001 NEC Corporation Patent Attorneys for the Applicant SPRUSON FERGUSON C! Page 89
AU57776/01A 1997-06-12 2001-08-02 Semiconductor device with an improved lead-chip adhesion structure and lead frame to be used therefor Abandoned AU5777601A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
AU57776/01A AU5777601A (en) 1997-06-12 2001-08-02 Semiconductor device with an improved lead-chip adhesion structure and lead frame to be used therefor

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP9-155090 1997-06-12
AU57776/01A AU5777601A (en) 1997-06-12 2001-08-02 Semiconductor device with an improved lead-chip adhesion structure and lead frame to be used therefor

Related Parent Applications (1)

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AU71840/98A Division AU736515B2 (en) 1997-06-12 1998-06-12 Semiconductor device with an improved lead-chip adhesion structure and lead frame to be used therefor

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AU5777601A true AU5777601A (en) 2001-10-04

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