AU536784B2 - Logic system for selectively reconfiguring an intersystem communication link - Google Patents

Logic system for selectively reconfiguring an intersystem communication link

Info

Publication number
AU536784B2
AU536784B2 AU52322/79A AU5232279A AU536784B2 AU 536784 B2 AU536784 B2 AU 536784B2 AU 52322/79 A AU52322/79 A AU 52322/79A AU 5232279 A AU5232279 A AU 5232279A AU 536784 B2 AU536784 B2 AU 536784B2
Authority
AU
Australia
Prior art keywords
communication link
logic system
intersystem communication
selectively reconfiguring
reconfiguring
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
AU52322/79A
Other languages
English (en)
Other versions
AU5232279A (en
Inventor
Kenneth Edgar Bruce
John William Conway
Ralph Michael Lombardo Jr.
Bruce Harold Tarbox
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Bull HN Information Systems Inc
Original Assignee
Honeywell Information Systems Italia SpA
Honeywell Information Systems Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Honeywell Information Systems Italia SpA, Honeywell Information Systems Inc filed Critical Honeywell Information Systems Italia SpA
Publication of AU5232279A publication Critical patent/AU5232279A/en
Application granted granted Critical
Publication of AU536784B2 publication Critical patent/AU536784B2/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4004—Coupling between buses
    • G06F13/4027—Coupling between buses using bus bridges
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4004—Coupling between buses
    • G06F13/4027—Coupling between buses using bus bridges
    • G06F13/404—Coupling between buses using bus bridges with address mapping
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4004—Coupling between buses
    • G06F13/4027—Coupling between buses using bus bridges
    • G06F13/4045—Coupling between buses using bus bridges where the bus bridge performs an extender function

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Bus Control (AREA)
  • Information Transfer Systems (AREA)
  • Small-Scale Networks (AREA)
  • Multi Processors (AREA)
AU52322/79A 1978-10-31 1979-10-30 Logic system for selectively reconfiguring an intersystem communication link Ceased AU536784B2 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US95638178A 1978-10-31 1978-10-31
US956381 1992-10-05

Publications (2)

Publication Number Publication Date
AU5232279A AU5232279A (en) 1980-05-15
AU536784B2 true AU536784B2 (en) 1984-05-24

Family

ID=25498165

Family Applications (1)

Application Number Title Priority Date Filing Date
AU52322/79A Ceased AU536784B2 (en) 1978-10-31 1979-10-30 Logic system for selectively reconfiguring an intersystem communication link

Country Status (4)

Country Link
JP (1) JPS5582342A (enrdf_load_stackoverflow)
AU (1) AU536784B2 (enrdf_load_stackoverflow)
BE (1) BE879667A (enrdf_load_stackoverflow)
CA (1) CA1147419A (enrdf_load_stackoverflow)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
AU592946B1 (en) * 1988-07-25 1990-01-25 Digital Equipment Corporation Network topology control method and apparatus
AU611735B2 (en) * 1987-12-21 1991-06-20 Honeywell Bull Inc. Apparatus and method for a data processing system having a peer relationship among a plurality of central processing units
AU624797B2 (en) * 1987-12-21 1992-06-25 Honeywell Bull Inc. Apparatus and method for access to user programs controlled by a first operating system by users interacting with a data processing system through a second operating system

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117056149B (zh) * 2023-10-08 2024-02-02 飞腾信息技术有限公司 一种内存测试方法、装置、计算设备及存储介质

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5152250A (ja) * 1974-11-01 1976-05-08 Hitachi Ltd Basukanketsugosochi
FR2296221A1 (fr) * 1974-12-27 1976-07-23 Ibm France Systeme de traitement du signal

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
AU611735B2 (en) * 1987-12-21 1991-06-20 Honeywell Bull Inc. Apparatus and method for a data processing system having a peer relationship among a plurality of central processing units
AU624797B2 (en) * 1987-12-21 1992-06-25 Honeywell Bull Inc. Apparatus and method for access to user programs controlled by a first operating system by users interacting with a data processing system through a second operating system
AU592946B1 (en) * 1988-07-25 1990-01-25 Digital Equipment Corporation Network topology control method and apparatus

Also Published As

Publication number Publication date
BE879667A (fr) 1980-02-15
JPS5582342A (en) 1980-06-21
AU5232279A (en) 1980-05-15
CA1147419A (en) 1983-05-31
JPH0155502B2 (enrdf_load_stackoverflow) 1989-11-24

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