AU5354399A

AU5354399A - Method of and switching facility for switching between two data streams without data loss

Info

Publication number: AU5354399A
Application number: AU53543/99A
Authority: AU
Inventors: Holger Herbrig; Jan-Hinnerk Dr. Reemtsma; Michael Wilhelm
Original assignee: Alcatel CIT SA; Alcatel SA
Current assignee: Alcatel Lucent SAS
Priority date: 1998-10-08
Filing date: 1999-10-08
Publication date: 2000-04-13
Also published as: CN1250992A; EP0993150A3; EP0993150A2; CA2284957A1; DE19846353A1; JP2000138716A

Description

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P/00/01i1 Regulation 3.2

AUSTRALIA

Patents Act 1990

ORIGINAL

COMPLETE SPECIFICATION STANDARD PATENT 6O S.

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SS

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Invention Title: Method of and switching facility for switching between two data streams without data loss The following statement is a full description of this invention, including the best method of performing it known to us: FH4PSYrDCE~NATPKfl2OQ9X1O16.6 Method of and Switching Facility for Switching BetweenTwo Data Streams without Data Loss This invention relates to a method of and a switching facility for switching from a first data stream to a time-shifted second data stream identical or similar in content to the first data stream.

Modern wireless access systems use fixed networks as transport networks. In the switching networks of the latter, particularly if, on the mobile side, handovers have occurred between two adjacent base stations, considerable differences in arrival time of data streams are caused as the data streams arrive over different paths. When switching between two otherwise error-free oo data streams, particularly during seamless handover procedures, these delay differences of data streams from adjacent base stations may cause errors, such as data losses or duplications.

To permit switching from one data stream to another, a so-called hitless switching system is known from JP 08065282 A in which the time offset between the two data streams is measured using a periodic clock signal generated for this purpose. By setting delays corresponding to this time offset, the time offset existing at the time of measurement is compensated for the future and switching to the new data stream is effected. If the time offset has meanwhile changed, however, errors (data losses or duplications) may occur.

Preferred embodiments of the invention to provide a method and a facility wherein the switching between two data streams is effected without introducing errors, particularly without data losses.

According to the invention, there is provided a method comprising the steps of comparing the two data streams for time offset and, if the time offset between the two data streams has been compensated for, switching from the compared first data stream to the compared second data stream.

The method may permit seamless handover at high data rates without data loss, supports macrodiversity, and has a wide range of application in telecommunications, data processing, and measurement technology. It can also work in the presence of uncorrelated erroneous data streams and is suitable for real-time operation, so that the exomplexity of the hardware required :i 1 5 for a real-time comparison of data streams can be greatly reduced. Throughput may be increased S and data losses and duplications can be avoided.

The simplest way to compensate for the time offset is to delay the data stream leading the other data stream.

In a preferred embodiment of the method, the two data streams are compared bit by bit in order to determine the time offset in the two data streams in u nits of bits. The result is then used to delay the data streams so that the time offset becomes zero. The comparison of the individual bits preferably takes place at different predefinable points of the two data streams.

.0.0 Preferred embodiments provide a switching facility of the kind mentioned at the beginning by providing a comparator circuit for comparing the two data streams for time offset, a compensator for compensating for a time offset, and a switching device for switching from the compared first data stream to the compared second data stream if the time offset has been compensated for.

With this switching facility, the same advantages as those mentioned above for the method may be achieved.

Freehills Patent Attorneys SYDCE\99280011.1 7 October 1999 Preferably, the switching facility comprises a controller for controlling the compensator in accordance with the time offset and for initiating the switching operation if the time offset has been compensated for. In particular, this controller should also be able to determine the date stream arriving earlier, so that this leading data stream can be delayed by the compensator (delay element).

Since only one of the two data streams needs to be delayed, it suffices in principle to provide a single delay element through which the respective data stream to be delayed is passed.

Preferably, however, the switching facility comprises one delay element per data stream which makes the respective relative time offset zero or introduces a defined delay between the two data streams.

particularly preferred are embodiments of the invention in which the comparator circuit comprises n registers each fed by the first data streams, one register fed by the second data stream, n comparators for comparing the n r .0 Freehills Patent Attorneys SYDCE\99280011.1 7 October 1999 registers bit by bit with said one register beginning with a different bit for each of the n registers with the respective nth bit), and a respective counter associated with each of the comparators for counting the number of identical bits. The counter with the highest count, which corresponds to the length of said one register, represents the time offset between the two data streams. An evaluation circuit processes the different counts into control and monitoring signals. This register arrangement requires, however, that the second data stream is delayed with respect to the first data stream.

To also cover cases where the first data stream is delayed with respect to the second, this comparator circuit may additionally comprise n registers each fed by the second data stream, one register fed by the first data stream, n comparators for comparing the n registers bit by bit with said one register beginning with a different bit for each of the n registers with the respective nth bit), and a respective *e*counter associated with each of the comparators for S* counting the number of identical bits. Such a comparator circuit can work independently of the relative positions *of the two data streams in time.

To minimize the number of comparators and counters as well as the complexity of the comparator circuit while o leaving the permitted offset-measuring range unchanged, each of the n registers is preceded by a respective delay "..*"element. These delay elements are set or programmable according to the frame structures ATM cells) of the two data streams in order to compare the data streams only payload block by payload block. The number of comparators and counters required can thus be reduced by a factor equal to the number of bits per frame -1.

The switching facility is particularly suited for use as a server for a digital exchange, for an asynchronous transfer mode (ATM) switch, with both data streams being diverted to the server for switching to the second data stream and the diversion being subsequently undone. This server principle ensures easy extensibility of existing systems.

The server can preferably be connected to the standard ports of the exchange, particularly of the ATM switch.

Further advantages of the invention are apparent from the following description and the accompanying drawings.

According to the invention, the aforementioned features and the features described below can be used alone or in arbitrary combinations. While particular embodiments of the invention are shown and described, it is to be understood that the description is made only by way of example and not as a limitation to the scope of the S"invention. In the drawings: Fig. 1 is a schematic block diagram of one embodiment "of the invention with a switching facility in an initial state in which a data connection exists from a first base station to a mobile station; Fig. 2 shows the switching facility of Fig. 1 during a handover phase in which a second, parallel data connection between the mobile station and a second base station is temporally adapted to the first data connection; Fig. 3 shows the switching facility of Fig. 1 in a final state following switchover to the second data connection; Fig. 4 is a schematic block diagram of a first embodiment of a comparator circuit for determining the time offset between two data streams; and Fig. 5 is a schematic block diagram of a second embodiment of a comparator circuit.

In Fig. i, the reference numeral 1 denotes a digital exchange (ATM switch) that can establish different data connections between its ports P1 to P6. In Fig. i, a data connection from port P1 to P3 is assumed for a connection from a mobile station 2 of one subscriber to a terminal 3 .of another subscriber, with P1 connected to a base station BSl serving the cell in which the mobile station 2 is located, and with P3 connected to the public switched telecommunications network PSTN, to which the terminal 3 is connected.

When the mobile subscriber passes from the cell with the base station BSI to the cell with the base station BS2, when a handover occurs in a mobile access network, two data streams with the same content exist at the exchange 1 for a transition period, namely the data stream dl applied at P1 and the new data stream d2 arriving at P2 from the base station BS2. These two data streams reach the ports P1 and P2 over different paths, and thus with different propagation delays.

In the present case, a control node CN of the exchange 1 is notified that a handover is occurring and that the two input ports P1, P2 and the output port P3 are affected.

As a result, the two data streams dl, d2 are diverted to a switching facility in the form of a server AS (seamless handover Assistant Server) (Fig. namely through ports P4 and P5 to ports ASP1 and ASP2 of the server AS. Via a switch S, which is in its normal position S1, the data stream dl in the server AS is transferred to port ASP3 and through port P6 to output port P3. At the same time, the direct connection between P1 and P3 in the exchange 1 is released, with the server controller SC receiving the necessary control information from the exchange 1 through the two CTR ports and from the server AS.

The server controller SC, which is fed with the two data streams dl, d2, is provided with a comparator circuit that measures the time offset between the two data streams dl and d2. According to the measured time offset, a delay T1 or T2 of a compensator 4 is set in the path of the leading data stream to compensate for the time o e offset. This compensator 4 is located ahead of the data 9* taps for the server controller SC. If the comparator circuit no longer registers a time offset, the server controller SC switches the switch S to position S2.

Instead of the compared data stream dl, the compared data stream d2 is now transferred to P3, this switching to the data stream d2 being synchronous with the data stream dl oo and thus causing no data loss.

*99*99 Next, the delay of the delay element T1 or T2 that is S° necessary for adaptation is cancelled. The server controller SC notifies the exchange 1 that the data stream adaptation has been successfully completed. In response thereto, the control node CN establishes a direct connection between port P2 and port P3 at the exchange 1 (Fig. 3) and simultaneously disestablishes the connections via ports P4, P5, and P6. The switch S returns to its normal position S1.

To handle parallel handovers, it is possible to utilize multiplex/demultiplex functions of the ports. In that case, the comparator circuit in the server controller

SC,

the compensator 4, and the switch S must be multiplied correspondingly.

The comparator circuit, which forms part of the server controller SC, may comprise two registers, one of length i *N and one of a shorter length which are fed with the data streams dl and d2, respectively. By comparing the contents of each cell of one register (the shorter one) with the N cells of the other register, the time offset between the compared data stream d2 and the compared data stream dl can be determined in units of bits. If the comparator circuit is designed to determine the crosscorrelation maximum, even a comparison of uncorrelated erroneous data streams is possible.

One embodiment of such a comparator circuit 5, which performs a bit-by-bit comparison of data streams, is shown in Fig. 4. The data streams to be compared, dl and d2, are fed into registers of different lengths, namely the data stream dl into registers Rla to Rna and the data coo; stream d2 into register Ra. Each of the registers Rla to Rna is followed by a comparator 6 and a counter Cla to Cna, the individual counts being evaluated by an evaluation circuit EC. In the comparators 6, the n registers Rla to Rna are compared bit by bit with the register Ra beginning, for example, with the respective nth bit, with the associated counter counting the respective number of identical bits, each of the comparators compares two data streams dl and d2 at different bit offsets. The counts of the individual counters correspond to the number of positive comparisons at a given time offset or bit offset between the two data streams.

The evaluation circuit EC processes the different counts into control and monitoring signals SIG for the server controller SC. After a finite measurement period, at a data offset of, one bit, the counter assigned to this offset, in this example the counter C2a, will show the highest result. This counter thus represents the time offset between the two data streams, expressed in bits.

According to the measured time offset, the data streams dl, d2 are delayed by the above-described delay elements T1, T2 to compensate for the time offset or introduce a defined delay between the data streams. The number n of registers Rla to Rna must be greater than the time offset or bit offset between the two data streams that is to be measured.

limitation of the example just described is that the comparator circuit 5 functions only if the data stream d2 is delayed with respect to the data stream dl. To be able to also cover those cases where the data stream dl is delayed with respect to the data stream d2, the expanded comparator circuit 7 shown in Fig. 5 comprises, in 9*9r addition to the comparison branch a, which is also present in Fig. 4, a further comparator branch b. In the comparison branch b, as opposed to the comparison branch a, the data stream d2 is fed into registers Rib to Rnb and the data stream dl into register Rb. As in the comparison branch a, the comparison of the two data streams is performed using comparators 8 and counters Clb to Cnb, whose counts are evaluated in the common evaluation circuit EC. Thus, this comparator circuit 7 works independently of the relative positions of the two data streams dl and d2.

To keep the number n of comparators 6, 8 and counters Cna, Cnb as well as the complexity of the comparator circuits 5, 7 to a minimum for the same permitted delaymeasuring range, the respective register branches a, b contain additional delay elements TP which are not connected to the comparator chain. These delay elements TP are programmable according to known frame structures ATM cells) of the data streams dl and d2. This can be illustrated by the example of ATM cells. The Ist bit in the data stream dl either corresponds with the 1st bit in the data stream d2 or it corresponds after at least 48 x 8 bits 384 bits after one payload block). It would therefore make little sense to evaluate bit offsets between 2 and 383 bits in that case. The number of comparators and counters can thus be reduced by a factor equal to the number of bits per frame minus 1.

O These programmable delay elements TP can be replaced by a single programmable counter that blocks the feeding into registers Rla and Ra or Rib and Rb according to the frame length.

The method according to the invention can also be carried out if the two data streams are synchronous. Furthermore, Sthe invention is also usable for switching between more than two data streams.

Claims

1. A method of switching from a first data stream to a time-shifted second data stream identical or similar in content to the first data stream and wherein the two data streams are compared for time offset, and that if the time offset between the two data streams has been compensated for, switching is effected from the compared first data stream to the compared second data stream.

2. A method as claimed in claim 1, wherein the data stream leading the other data stream is delayed.

3. A method as claimed in claim 1 or claim 2, wherein the two data streams are compared bit by bit.

4. A method as claimed in claim 3, wherein the comparison of the individual bits takes place at different predefinable points of the two data streams.

A switching facility for switching from a first data stream to a time-shifted second data stream identical or similar in content to the first data stream, particularly for carrying out the method according to any one of the preceding claims, said switching facility comprising: o a comparator circuit for comparing the two data streams for time offset; a compensator for compensating for a time offset; and a switching device for switching from the compared first data stream to the compared 20 second data stream if the time offset has been compensated for.

6. A switching facility as claimed in claim 5, wherein a controller is provided for controlling the compensator in accordance with the time offset.

7. A switching facility as claimed in claim 5 or 6, wherein the data stream leading the other data stream is delayed by the compensator.

8. A switching facility as claimed in any one of the claims 5 to 7, wherein the compensator comprises at least one delay element for each data stream.

9. A switching facility as claimed in any one of claims 5 to 8, wherein the comparator circuit comprises: Freehills Patent Attorneys SYDCA\99280011.1 8 October 1999 n registers each fed by the first data stream; one register fed by the second data stream; n comparators for comparing the n registers bit by bit with said one register beginning with a different bit for each of the n registers; and a respective counter associated with each of the comparators for counting the number of identical bits.

A switching facility as claimed in claim 9, wherein the comparator circuit further comprises; n registers each fed by the second data stream; one register fed by the first data stream; n comparators for comparing the n registers bit by bit with said one register beginning with a different bit for each of the n registers; and a respective counter associated with each of the comparators for counting the number of identical bits.

11. A switching facility as claimed in claim 9 or 10, wherein each of the n registers is preceded by a delay element.

12. A switching facility as claimed in any one of claims 5 to 11, wherein the switching facility is used as a server for a digital exchange, with both data streams being diverted to the server for switching to the second data stream and the diversion being :•20 subsequently undone.

13. A switching facility as claimed in claim 12, wherein the server is connected to the standard ports of the digital exchange, particularly of an ATM switch.

14. A switching facility for switching from a first data stream to a time-shifted second data stream; substantially as hereinbefore described with reference to the accompanying drawings. Freehills Patent Attorneys SYDCA\99280011.1 8 October 1999 13 A method substantially as hereinbefore described with reference to the accompanying drawings. Dated this 8th day of October 1999 ALCATEL by its attorneys Freehills Patent Attorneys Freehills Patent Attorneys SYDCA\99280011.1 8 October 1999