AU3467500A - Polycrystalline module and method for producing a semiconductor module - Google Patents
Polycrystalline module and method for producing a semiconductor moduleInfo
- Publication number
- AU3467500A AU3467500A AU34675/00A AU3467500A AU3467500A AU 3467500 A AU3467500 A AU 3467500A AU 34675/00 A AU34675/00 A AU 34675/00A AU 3467500 A AU3467500 A AU 3467500A AU 3467500 A AU3467500 A AU 3467500A
- Authority
- AU
- Australia
- Prior art keywords
- module
- producing
- polycrystalline
- semiconductor
- semiconductor module
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02612—Formation types
- H01L21/02617—Deposition types
- H01L21/02623—Liquid deposition
- H01L21/02625—Liquid deposition using melted materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L24/20—Structure, shape, material or disposition of high density interconnect preforms
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L24/19—Manufacturing methods of high density interconnect preforms
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/0132—Binary Alloys
- H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Nitrogen And Oxygen Or Sulfur-Condensed Heterocyclic Ring Systems (AREA)
Applications Claiming Priority (5)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
RO99105254 | 1999-03-23 | ||
RU99105254A RU2139598C1 (en) | 1999-03-23 | 1999-03-23 | Process of manufacture of semiconductor module |
RU99105255A RU2140688C1 (en) | 1999-03-23 | 1999-03-23 | Multichip module |
RO99105255 | 1999-03-23 | ||
PCT/RU2000/000093 WO2000057477A1 (en) | 1999-03-23 | 2000-03-22 | Polycrystalline module and method for producing a semiconductor module |
Publications (1)
Publication Number | Publication Date |
---|---|
AU3467500A true AU3467500A (en) | 2000-10-09 |
Family
ID=26654005
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
AU34675/00A Abandoned AU3467500A (en) | 1999-03-23 | 2000-03-22 | Polycrystalline module and method for producing a semiconductor module |
Country Status (2)
Country | Link |
---|---|
AU (1) | AU3467500A (en) |
WO (1) | WO2000057477A1 (en) |
Family Cites Families (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS49131863U (en) * | 1973-03-10 | 1974-11-13 | ||
JPS6022396A (en) * | 1983-07-19 | 1985-02-04 | 日本電気株式会社 | Circuit board |
US4984731A (en) * | 1989-10-05 | 1991-01-15 | Matsushita Electric Industrial Co., Ltd. | Method of packaging electronic component parts using a eutectic die bonder |
RU2003207C1 (en) * | 1990-12-26 | 1993-11-15 | Институт точной механики и вычислительной техники им.С.А.Лебедева РАН | Process of manufacture of hybrid integrated circuit |
RU2091906C1 (en) * | 1994-04-28 | 1997-09-27 | Акционерное общество открытого типа "Научно-исследовательский центр электронной вычислительной техники" | Multichip module |
-
2000
- 2000-03-22 AU AU34675/00A patent/AU3467500A/en not_active Abandoned
- 2000-03-22 WO PCT/RU2000/000093 patent/WO2000057477A1/en active Search and Examination
Also Published As
Publication number | Publication date |
---|---|
WO2000057477A1 (en) | 2000-09-28 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
MK6 | Application lapsed section 142(2)(f)/reg. 8.3(3) - pct applic. not entering national phase |