AU3144395A - Digital circuit topology offering an improved power delay product - Google Patents

Digital circuit topology offering an improved power delay product

Info

Publication number
AU3144395A
AU3144395A AU31443/95A AU3144395A AU3144395A AU 3144395 A AU3144395 A AU 3144395A AU 31443/95 A AU31443/95 A AU 31443/95A AU 3144395 A AU3144395 A AU 3144395A AU 3144395 A AU3144395 A AU 3144395A
Authority
AU
Australia
Prior art keywords
digital circuit
improved power
circuit topology
power delay
delay product
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
AU31443/95A
Inventor
William H Herndon
Graham Y Mostyn
John P Moussouris
Timothy B Robinson
Geert P Rosseel
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Microunity Systems Engineering Inc
Original Assignee
Microunity Systems Engineering Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Microunity Systems Engineering Inc filed Critical Microunity Systems Engineering Inc
Publication of AU3144395A publication Critical patent/AU3144395A/en
Abandoned legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0008—Arrangements for reducing power consumption
    • H03K19/0013—Arrangements for reducing power consumption in field effect transistor circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
    • H03K19/018507—Interface arrangements

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Logic Circuits (AREA)
AU31443/95A 1994-07-25 1995-07-25 Digital circuit topology offering an improved power delay product Abandoned AU3144395A (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US28038294A 1994-07-25 1994-07-25
US280382 1994-07-25
PCT/US1995/009349 WO1996003807A1 (en) 1994-07-25 1995-07-25 Digital circuit topology offering an improved power delay product

Publications (1)

Publication Number Publication Date
AU3144395A true AU3144395A (en) 1996-02-22

Family

ID=23072849

Family Applications (1)

Application Number Title Priority Date Filing Date
AU31443/95A Abandoned AU3144395A (en) 1994-07-25 1995-07-25 Digital circuit topology offering an improved power delay product

Country Status (2)

Country Link
AU (1) AU3144395A (en)
WO (1) WO1996003807A1 (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100468430B1 (en) * 2001-06-13 2005-01-27 조영봉 Preparation method of pure sludge or pure liquid for resource recovery
KR20030003347A (en) * 2001-06-30 2003-01-10 황석훈 The System and Method of Purifying Heavy Metal Wastewater

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3991379A (en) * 1975-06-03 1976-11-09 United Technologies Corporation Logic level decoding circuit
US4163209A (en) * 1977-09-28 1979-07-31 Harris Corporation Technique for controlling memoryful non-linearities
US5025251A (en) * 1989-06-29 1991-06-18 Motorola, Inc. Self-tuning direct coupled data limiter of a battery saver type paging receiver
US5425056A (en) * 1993-03-23 1995-06-13 Motorola, Inc. Method and apparatus for generating threshold levels in a radio communication device for receiving four-level signals

Also Published As

Publication number Publication date
WO1996003807A1 (en) 1996-02-08

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