AU2017377949B2 - Clock gating enable generation - Google Patents

Clock gating enable generation Download PDF

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Publication number
AU2017377949B2
AU2017377949B2 AU2017377949A AU2017377949A AU2017377949B2 AU 2017377949 B2 AU2017377949 B2 AU 2017377949B2 AU 2017377949 A AU2017377949 A AU 2017377949A AU 2017377949 A AU2017377949 A AU 2017377949A AU 2017377949 B2 AU2017377949 B2 AU 2017377949B2
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AU
Australia
Prior art keywords
clock
pipeline
clock signal
packets
input
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
AU2017377949A
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English (en)
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AU2017377949A1 (en
Inventor
Adam Andrew Zerwick
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Qualcomm Inc
Original Assignee
Qualcomm Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Qualcomm Inc filed Critical Qualcomm Inc
Publication of AU2017377949A1 publication Critical patent/AU2017377949A1/en
Application granted granted Critical
Publication of AU2017377949B2 publication Critical patent/AU2017377949B2/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

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Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/08—Clock generators with changeable or programmable clock frequency
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3234—Power saving characterised by the action undertaken
    • G06F1/3237—Power saving characterised by the action undertaken by disabling clock generation or distribution
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/36—Prevention of errors by analysis, debugging or testing of software
    • G06F11/362—Debugging of software
    • G06F11/3648—Debugging of software using additional hardware
    • G06F11/3656—Debugging of software using additional hardware using a specific debug interface
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/32—Circuit design at the digital level
    • G06F30/327—Logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • G06F30/396—Clock trees
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/44—Arrangements for executing specific programs
    • G06F9/455—Emulation; Interpretation; Software simulation, e.g. virtualisation or emulation of application or operating system execution engines
    • G06F9/45504—Abstract machines for programme code execution, e.g. Java virtual machine [JVM], interpreters, emulators
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2117/00—Details relating to the type or aim of the circuit design
    • G06F2117/04—Clock gating
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2119/00—Details relating to the type or aim of the analysis or the optimisation
    • G06F2119/06—Power analysis or power optimisation
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2119/00—Details relating to the type or aim of the analysis or the optimisation
    • G06F2119/12—Timing analysis or timing optimisation
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Software Systems (AREA)
  • Geometry (AREA)
  • Evolutionary Computation (AREA)
  • Quality & Reliability (AREA)
  • Advance Control (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)
  • Power Sources (AREA)
  • Image Processing (AREA)
  • Information Transfer Systems (AREA)
AU2017377949A 2016-12-13 2017-11-27 Clock gating enable generation Active AU2017377949B2 (en)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US201662433547P 2016-12-13 2016-12-13
US62/433,547 2016-12-13
US15/666,107 US10761559B2 (en) 2016-12-13 2017-08-01 Clock gating enable generation
US15/666,107 2017-08-01
PCT/US2017/063306 WO2018111526A1 (en) 2016-12-13 2017-11-27 Clock gating enable generation

Publications (2)

Publication Number Publication Date
AU2017377949A1 AU2017377949A1 (en) 2019-05-16
AU2017377949B2 true AU2017377949B2 (en) 2021-08-19

Family

ID=62489120

Family Applications (1)

Application Number Title Priority Date Filing Date
AU2017377949A Active AU2017377949B2 (en) 2016-12-13 2017-11-27 Clock gating enable generation

Country Status (11)

Country Link
US (1) US10761559B2 (enExample)
EP (1) EP3555726B1 (enExample)
JP (1) JP6746791B2 (enExample)
KR (1) KR102143089B1 (enExample)
CN (1) CN110073311B (enExample)
AU (1) AU2017377949B2 (enExample)
BR (1) BR112019010936A2 (enExample)
ES (1) ES2801598T3 (enExample)
HU (1) HUE050331T2 (enExample)
TW (1) TWI722258B (enExample)
WO (1) WO2018111526A1 (enExample)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11114057B2 (en) * 2018-08-28 2021-09-07 Samsung Display Co., Ltd. Smart gate display logic
US11099602B2 (en) * 2019-04-30 2021-08-24 International Business Machines Corporation Fault-tolerant clock gating
CN112462845B (zh) * 2020-11-25 2024-06-18 海光信息技术股份有限公司 数据传输时钟控制电路、方法和处理器
US12081214B2 (en) * 2021-12-07 2024-09-03 Mediatek Inc. Clock gating cells

Citations (2)

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US20040032855A1 (en) * 2002-08-19 2004-02-19 Nec Corporation Communication data processing circuit
EP2124130A2 (en) * 2008-05-19 2009-11-25 NEC Corporation Packet processor, packet control method, and packet control program

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US6636074B2 (en) 2002-01-22 2003-10-21 Sun Microsystems, Inc. Clock gating to reduce power consumption of control and status registers
JP2004274099A (ja) 2003-03-05 2004-09-30 Nec Corp パケット処理回路
TWI253556B (en) * 2003-06-11 2006-04-21 Faraday Tech Corp Pipeline-based circuit with a postponed clock-gating mechanism for reducing power consumption and related driving method thereof
US6822481B1 (en) * 2003-06-12 2004-11-23 Agilent Technologies, Inc. Method and apparatus for clock gating clock trees to reduce power dissipation
US7594200B2 (en) * 2005-12-19 2009-09-22 International Business Machines Corporation Method for finding multi-cycle clock gating
US7949887B2 (en) * 2006-11-01 2011-05-24 Intel Corporation Independent power control of processing cores
US7802118B1 (en) * 2006-12-21 2010-09-21 Nvidia Corporation Functional block level clock-gating within a graphics processor
US7797561B1 (en) * 2006-12-21 2010-09-14 Nvidia Corporation Automatic functional block level clock-gating
US8073669B2 (en) * 2007-08-21 2011-12-06 International Business Machines Corporation Method and apparatus for detecting clock gating opportunities in a pipelined electronic circuit design
US7861192B2 (en) * 2007-12-13 2010-12-28 Globalfoundries Inc. Technique to implement clock-gating using a common enable for a plurality of storage cells
EP3258386B1 (en) * 2009-01-12 2019-05-01 Rambus Inc. Mesochronous signaling system with clock-stopped low power mode
JP2011061457A (ja) * 2009-09-09 2011-03-24 Elpida Memory Inc クロック生成回路及びこれを備える半導体装置並びにデータ処理システム
US9557795B1 (en) 2009-09-23 2017-01-31 Xilinx, Inc. Multiprocessor system with performance control based on input and output data rates
EP2360548A3 (en) 2010-02-12 2013-01-30 Blue Wonder Communications GmbH Method and device for clock gate controlling
US8533648B2 (en) * 2010-05-13 2013-09-10 Oracle International Corporation Automatic clock-gating propagation technique
US9444440B2 (en) * 2011-06-30 2016-09-13 Stmicroelectronics International N.V. Transition detector
JP2013125436A (ja) 2011-12-15 2013-06-24 Panasonic Corp 画像処理回路および半導体集積回路
US9323315B2 (en) 2012-08-15 2016-04-26 Nvidia Corporation Method and system for automatic clock-gating of a clock grid at a clock source
US20140225655A1 (en) * 2013-02-14 2014-08-14 Qualcomm Incorporated Clock-gated synchronizer
EP3053003A4 (en) * 2013-09-30 2017-05-24 Intel Corporation Early wake-warn for clock gating control
GR20130100707A (el) * 2013-12-23 2015-07-31 Arm Limited, Μεταφραση διευθυνσης σε μια συσκευη επεξεργασιας δεδομενων
US9154130B2 (en) * 2014-01-14 2015-10-06 Analog Devices, Inc. Four-state input detection circuitry
US10204532B2 (en) * 2015-09-25 2019-02-12 Intel Corporation Multiple input cryptographic engine

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040032855A1 (en) * 2002-08-19 2004-02-19 Nec Corporation Communication data processing circuit
EP2124130A2 (en) * 2008-05-19 2009-11-25 NEC Corporation Packet processor, packet control method, and packet control program

Also Published As

Publication number Publication date
TW201826710A (zh) 2018-07-16
CN110073311B (zh) 2023-03-24
BR112019010936A2 (pt) 2019-10-01
US20180164846A1 (en) 2018-06-14
JP2020513628A (ja) 2020-05-14
EP3555726A1 (en) 2019-10-23
EP3555726B1 (en) 2020-04-22
CN110073311A (zh) 2019-07-30
AU2017377949A1 (en) 2019-05-16
WO2018111526A1 (en) 2018-06-21
JP6746791B2 (ja) 2020-08-26
TWI722258B (zh) 2021-03-21
ES2801598T3 (es) 2021-01-11
HUE050331T2 (hu) 2020-11-30
KR102143089B1 (ko) 2020-08-10
US10761559B2 (en) 2020-09-01
KR20190094364A (ko) 2019-08-13

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