AU2009254403A1

AU2009254403A1 - An electronic detonator control chip and a detecting method of its connection correctness

Info

Publication number: AU2009254403A1
Application number: AU2009254403A
Authority: AU
Inventors: Huaping Lai; Fengguo Li; Xing Liu; Jinglong Yan; Xianyu Zhang
Original assignee: Beijing Ebtech Tech Co Ltd
Current assignee: Beijing Ebtech Tech Co Ltd
Priority date: 2008-06-04
Filing date: 2009-06-02
Publication date: 2009-12-10
Anticipated expiration: 2029-06-02
Also published as: AU2009254403B2; WO2009146645A1; ZA201100031B; CN101338995B; CN101338995A

Description

An Electronic Detonator Control Chip and a Detecting Method of its Connection Correctness Technical Field The present invention relates to the field of initiating explosive devices, in particular to an electronic detonator control chip and a detecting method of its connection correctness. Background of the Invention Since 1980's, Japan, Australia, Europe and other developed countries or districts have begun to study the technology of electronic detonators. Great progress in the electronic detonator technology has been made with rapid development of electronic technology, micro-electronics technology, and information technology, Application experiment and market promotion of the electronic detonator have been conducted out since the late 1990s. As the core component of the electronic detonator, the performance of the electronic detonator control chip directly affects the performance of the electronic detonator. The electronic detonator control chip disclosed in Chinese Patent ZLO3156912.9 and Chinese Patent ZL200820111269.7 realizes the basic functions of two-wire non-polarity connection, bidirectional communication between the electronic detonator and its external detonation apparatus, identity code built-in, controllability of detonation process, electronic delay and so on, which has already achieved essential advancement comparing with traditional detonators. But since the electronic detonator control chip described above doesn't have the function of internal Built-in Test (BIT), the veracity and reliability of the connections of the chip itself and the components at the external of the chip becomes undetectable. So once the chip is assembled into the detonator shell in the process of manufacturing of the electronic detonator, detecting the connection correctness of the components connected to the chip, especially the connection correctness of the ignition unit will become impossible, resulting in latent dangers in the use of electronic detonators. In Chinese Patent ZL200420034635.5 in which a digital timing circuit and external separated electronic elements are used to realize the function of electronic detonators, an electronic switch is used to interrupt the connection between the ignition unit and the detonator wires, so the electronic detonator disclosed in the above patent still hasn't realized the function of detecting the connection correctness of the ignition unit. Furthermore, Chinese Patent ZL98210324.7 discloses a subsection-delay detonator in which the fuse bridge is further extended to the detonator wires via a current-limiting resistor, realizing the function of external test after manufacture. But in this technical solution, there is a direct current connection between the ignition unit and the detonator wires, thus affecting the security performance of the detonator such as resistance to static 1 P39337 electricity and radio frequency. In addition, it will be impossible to detect the connection correctness of the ignition unit after the detonation network is arranged completely either. Another defect existed both in the aforementioned Patent ZL200420034635.5 and Patent ZL98210324.7 lies in: the detonator will ignite whenever and wherever powered. So the detonation process of such detonator is uncontrollable, and the problem of social security can not be solved either. The micro-electronic cipher delay unit disclosed in Chinese Patent ZL200620094002.2 is still impossible to detect the connection correctness of the ignition unit of the detonator. Summary of the Invention The purpose of the present invention is to solve the defects of the prior art described above, and to provide an electronic detonator control chip which can realize repeatable detecting online of connection correctness of the chip itself and its external components, and a method to detect the connection correctness of such a chip, thus improving the reliability of the electronic detonator in manufacture and use without any effect on using security of the electronic detonator products. The technical solution of the present invention which is based on the electronic detonator control chip disclosed in the Patent ZLO3156912.9 and the Patent ZL200820111269.7 can be described as follows: The electronic detonator control chip in the present invention includes a charging circuit, a charging control circuit, a power supply management circuit, a firing control circuit, a logic control circuit, and a safe discharging circuit. The charging control circuit and the safe discharging circuit extend to the exterior of the chip together, forming a connecting end; and the connecting end further connects with the storage unit and the ignition unit at the external of the chip. Especially, the present chip further includes a detecting circuit. The detecting circuit starts or stops detecting under the control of a control signal output by the logic control circuit, and outputs a detecting signal gained from the connecting end to the logic control circuit; and the logic control circuit outputs the control signal to the detecting circuit to control its starting or stopping, reads the detecting signal output by the detecting circuit, and judges whether or not the circuit connections of the charging control circuit, the firing control circuit, the safe discharging circuit, the storage unit, the ignition unit, or loops consisted of the combination of the above five components are correct according to the detecting signal. The present chip can further include a communication interface circuit, a rectifier bridge circuit, a non-volatile memory, a reset circuit, and a clock circuit according to the technical solution above. Wherein one end of the charging circuit is connected to the rectifier bridge circuit; the other end leads to the power supply management circuit, and extends to the exterior of the chip to form a set of first pin. A first of the charging control circuit is connected to the rectifier bridge circuit, a second is connected to the logic control circuit; a third end of the charging control circuit is connected to the safe discharging circuit, and extends to the exterior of the chip to form the connecting end. A 2 P39337 first end of the safe discharging circuit is connected to the logic control circuit, a second end is grounded, and a third end is connected to the connecting end. A first end of the power supply management circuit is connected to the first pin, a second end is grounded, and a third end extends to the exterior of the chip, forming a set of third pin acting as a power supply output terminal. A first end of the firing control circuit is grounded, a second end extends to the exterior of the chip to form a set of fourth pin, and a third end is connected to the logic control circuit. One end of the logic control circuit is connected to the clock circuit, one end is connected to the third pin, one end is grounded, one end is connected to the non-volatile memory, one end is connected to the communication interface circuit, one end is connected to the reset circuit, one end is connected to the safe discharging circuit, one end is connected to the firing control circuit, and another end is connected to the charging control circuit. Especially, a power supply input terminal of the detecting circuit in the chip is connected to the power supply output terminal of the power supply management circuit, and the detecting circuit is powered by the power supply management circuit; a detecting signal input terminal of the detecting circuit is connected to the charging control circuit and the safe discharging circuit, and is connected to the connecting end within the chip; another terminal of the detecting circuit is grounded; and another terminal of the detecting circuit is connected to the logic control circuit. As one embodiment of the present invention, the detecting circuit includes a detecting control circuit, a comparator, and a first PMOS transistor. a power supply input terminal of the detecting control circuit is connected with the source and the substrate of the first PMOS transistor, and they are connected to the third pin jointly, forming the power supply input terminal of the detecting circuit, being powered by the power supply management circuit. A control terminal of the detecting control circuit is connected to the logic control circuit, receiving the control signal sent by the logic control circuit. An input terminal of the detecting control circuit is connected to the safe discharging circuit and the charging control circuit, and is connected to the connecting end jointly, forming the detecting signal input terminal of the detecting circuit. An output terminal of the detecting control circuit is connected to the signal input terminal of the comparator, while another terminal of the detecting control circuit is grounded. The grid of the first PMOS transistor is connected to the logic control circuit, and its drain is connected to the power supply input terminal of the comparator. The signal output terminal of the comparator leads to the logic control circuit, forming the detecting signal output terminal of the detecting circuit, and the other end of the comparator is grounded. As another embodiment of the present invention, the detecting circuit includes a detecting control circuit, a comparator, and a first PMOS transistor. A control terminal of the detecting control circuit is connected to the logic control circuit, receiving the control signal sent by the logic control circuit. An input terminal of the detecting control circuit is connected to the safe discharging circuit and the charging control circuit, and is jointly connected to the connecting end, forming the detecting signal input terminal of the detecting circuit. An output terminal of the detecting control circuit is connected to the 3 P39337 signal input terminal of the comparator, and another terminal of the detecting control circuit is grounded. The source and the substrate of the first PMOS transistor are connected to the third pin, forming the power supply input terminal of the detecting circuit, being powered by the power supply management circuit. The grid of the first PMOS transistor is connected to the logic control circuit, and its drain is connected to the power supply input terminal of the comparator. The signal output terminal of the comparator leads to the logic control circuit, forming the detecting signal output terminal of the detecting circuit, and the other end of the comparator is grounded. The advantages of the two embodiments above lie in: 1. As the detecting circuit is located inside the electronic detonator control chip, the detecting process will depend only on the connection state of the internal electronic components of the electronic detonator. This realizes detecting of the connection correctness of the chip, and the ignition unit and the storage unit at the external of the chip after manufacture of the electronic detonator is completed. 2. In the aforementioned embodiments, the detecting circuit is located inside the chip, and outputs the signal through the connecting end to the detecting signal input terminal of the detecting circuit within the chip, thus maintaining the connection interruption between the ignition unit and the detonator wires, so that the problem of detectability of the electronic detonator is solved with no effect on the security of use and storage of the detonators. 3. The detecting process of the detecting circuit is under the control of the logic control circuit, realizing repeatable detecting online of the charging control circuit, the firing control circuit, the safe discharging circuit, the storage unit, the ignition unit, and loops consisted of the combination of the above five components, realizing repeatable testing online of the working state of the digital logic circuit meanwhile, thus improving the reliability of the use of the electronic detonator. 4. As the detecting circuit needs to consume the energy stored in the storage unit at the external of the chip, controlling the detecting circuit to work or not, that is, controlling the detecting circuit to start or stop detecting by using the logic control circuit, can avoid consumption of the energy stored in the storage unit caused by the detecting circuit in the state of non-detecting. As a first embodiment, the detecting control circuit includes a first resistor, a second resistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a first NMOS transistor, a second NMOS transistor, and a third NMOS transistor. The source and the substrate of the second PMOS transistor are connected to the third pin, being powered by the power supply management circuit; the grid of the second PMOS transistor is connected to the logic control circuit, with both connected to the grid of the first NMOS transistor and the grid of the third NMOS transistor jointly; the drain of the second PMOS transistor is connected to the drain of the first NMOS transistor and the grid of the second NMOS transistor. The source and the substrate of the third PMOS transistor, the source and the substrate of the fourth PMOS transistor are jointly connected to the safe discharging circuit and the charging control circuit, and are connected to the connecting end, forming the input 4 P39337 terminal of the detecting control circuit; the drain of the third PMOS transistor is connected to the drain of the second NMOS transistor and the grid of the fourth PMOS transistor; the grid of the third PMOS transistor is connected to the drain of the fourth PMOS transistor and the drain of the third NMOS transistor, and they are connected to one end of the first resistor together. The source and the substrate of the first NMOS transistor, the source and the substrate of the second NMOS transistor, and the source and the substrate of the third NMOS transistor are grounded together. A first end of the first resistor is connected to the grid of the third PMOS transistor, the drain of the fourth PMOS transistor, and the drain of the third NMOS transistor jointly; a second end of the first resistor is connected to the signal input terminal of the comparator, forming the output terminal of the detecting control circuit, and the second end is grounded via the second resistor. The advantages of the first embodiment of the detecting control circuit lie in: 1. The control of signal transmission between the detecting signal input terminal of the detecting circuit and the signal input terminal of the comparator is realized. The signal input from the detecting signal input terminal of the detecting circuit is the voltage signal of the ignition capacitor in the storage unit which is input to the detecting circuit via the connecting end. As the voltage of the voltage signal is much higher than the operating voltage of the logic control circuit, the detecting control circuit realizes the control of the transmission of the signal with higher voltage by the signal with lower voltage output by the logic control circuit, thus realizing the insulation of the signal with high voltage in the state of non-detecting, avoiding the transmission of the signal with high voltage to the signal input terminal of the comparator, and reducing the requirement to voltage resistance of the comparator. 2. With the characteristic of voltage division of the first resistor and the second resistor, the highest detecting voltage of the detecting circuit can be set to the voltage that is lower than the safe voltage which is needed by the ignition unit to ignite and stored in the ignition capacitor of the storage unit. 3. Leak current caused by the first resistor and the second resistor of the detecting circuit in the state of non-operating is avoided, so is the consumption of the ignition energy stored in the storage unit caused by the existence of the leak current. As a second embodiment, the detecting control circuit includes a fifth PMOS transistor, a fourth NMOS transistor, a first resistor, a second resistor, and a third resistor. The source and the substrate of the fifth PMOS transistor are connected to one end of the third resistor, and they are jointly connected to the safe discharging circuit and the charging control circuit; this end of the third resistor also leads to the connecting end, forming the input terminal of the detecting control circuit; the drain of the fifth PMOS transistor is connected to one end of the first resistor; the grid of the fifth PMOS transistor is connected to the other end of the third resistor, and they are connected to the drain of the fourth NMOS transistor jointly. The source and the substrate of the fourth NMOS transistor are grounded, its grid is connected with the logic control circuit, and its drain is connected with the grid of the fifth PMOS transistor. One end of the second resistor is grounded; the other end of the second resistor 5 P39337 is connected to the other end of the first resistor, and they are connected to the signal input terminal of the comparator jointly, forming the output terminal of the detecting control circuit. A pull-up resistor, the third resistor, which is connected to the detecting signal input terminal of the detecting circuit, is used to realize the control of the transmission of the signal with higher voltage by the signal with lower voltage output by the logic control circuit, thus reducing the requirement to voltage resistance of the comparator. This embodiment realizes the function of the detecting control circuit, and is simple to implement relatively, because the detecting control circuit in this embodiment does not need to be powered by the power supply management circuit. As a third embodiment, the detecting control circuit includes a first resistor, a second resistor, and a fifth NMOS transistor. The source and the substrate of the fifth NMOS transistor are grounded, its grid is connected with the logic control circuit, and its drain is connected with one end of the second resistor. The other end of the second resistor is connected with one end of the first resistor, and they lead to the signal input terminal of the comparator together, forming the output terminal of the detecting control circuit. The other end of the first resistor is connected to the safe discharging circuit and the charging control circuit, and this end also leads to the connecting end, forming the input terminal of the detecting control circuit. This embodiment renders the control easier by controlling the low level end of the first resistor and the second resistor that act as voltage division resistors. The comparator mentioned above may include a voltage comparator, a fourth resistor, a fifth resistor, and a sixth resistor. The fourth resistor is connected between the in-phase input terminal and the power supply input terminal of the voltage comparator, and they are connected to the drain of the first PMOS transistor jointly. The fifth resistor is connected between the in-phase input terminal of the voltage comparator and the ground, while the sixth resistor crosses over the in-phase input terminal and the output terminal of the voltage comparator. The out-phase input terminal of the voltage comparator is connected to the output terminal of the detecting control circuit, forming the signal input terminal of the comparator; the output terminal of the voltage comparator leads to the logic control circuit, forming the signal output terminal of the comparator, and the other terminal of the voltage comparator is grounded. The advantages of the embodiment of the comparator lie in: on the one hand, the three resistors, the fourth resistor, the fifth resistor, and the sixth resistor, are used to form a voltage division net, so that the comparator's threshold voltage which is the voltage that renders the output of the comparator overturn when the input of the comparator changes from low to high or from high to low can be set discretionarily, thus improving anti-jamming ability of the detecting circuit; on the other hand, the comparator transforms analog signals input from the signal input terminal of the comparator to digital signals and outputs digital signals to the logic control circuit, so that the logic control circuit can conveniently judge the detecting state. As a third embodiment of the present invention, the detecting circuit could be a Schmitt inverter. The power supply input terminal of the Schmitt inverter is connected with the third pin and the power supply management 6 P39337 circuit, forming the power supply input terminal of the detecting circuit. The input terminal of the Schmitt inverter is connected with the charging control circuit, the safe discharging circuit, and the connecting end, forming the detecting signal input terminal of the detecting circuit. The output terminal of the Schmitt inverter leads to the logic control circuit, forming the detecting signal output terminal of the detecting circuit. One end of the Schmitt inverter is grounded. The advantages of using the Schmitt inverter as the detecting circuit lie in: the Schmitt inverter forms a threshold switching circuit with the characteristic of sharp changeable input-output. Comparing with inverters composed of other circuits, on the one hand, the Schmitt inverter can adjust the input signal with slow changes to rectangle impulse with steep edges which is convenient for the logic control circuit to identify; on the other hand, the Schmitt inverter can prevent changes of the output voltage caused by noises of the input voltage, thus improving the anti-jamming and anti-noise ability of the circuit. The present invention also provides a method of detecting the electronic detonator control chip, which is carried out in accordance with the following steps: Step 1, detecting the default initial working states of the charging control circuit, the safe discharging circuit, and the firing control circuit: if any of the default initial working states is abnormal, Step 6 is executed; if all the default initial working states are normal, Step 2 is executed; Step 2, detecting the working state of the charging loop composed of the charging control circuit and the storage unit: if the working state of the charging loop is detected to be normal, Step 3 is executed; if not, Step 6 is executed; Step 3, detecting the working state of one of the following two loops, which are the firing loop composed of the storage unit, the ignition unit, and the firing control circuit, and the safe discharging loop composed of the storage unit and the safe discharging circuit: if the working state of the loop detected is detected to be normal, Step 4 is executed; if not, Step 6 is executed; Step 4, charging the storage unit to a predetermined high level voltage; Step 5, detecting the other loop that has not been detected between the firing loop and the safe discharging loop mentioned in Step 3; Step 6, sending control signals to the charging control circuit, the safe discharging circuit, and the firing control circuit respectively to render them return to their respective default initial working state; then ending this detecting method. The default initial working states mentioned in Step 1 are normal when the charging control circuit is in a non-charging state, the safe discharging circuit is in a discharging state, and the firing control circuit is in a fire-forbidden state. While detecting the default initial working states in Step 1 could be carried out by detecting the voltage of the connecting end: if the voltage of the connecting end is higher than a predetermined high level voltage, the logic control circuit will judge that the default initial working states are 7 P39337 abnormal; if the voltage of the connecting end is not higher than the predetermined high level voltage, the logic control circuit will judge that the default initial working states are normal. According to the detecting method above, Step 2 which realizes the detecting on the working state of the charging loop could be carried out in accordance with the following steps: Step A, the logic control circuit sends a control signal to the safe discharging circuit, rendering it in a non-discharging state; the logic control circuit also sends a control signal to the charging control circuit, rendering it in a charging state; Step B, the logic control circuit reads the detecting signal from the detecting signal output terminal, and lasts for a predetermined minimal charging time: before the minimal charging time is reached, if the detecting signal changes, the logic control circuit sets a detecting abnormal sign to the charging loop detecting, then ends this detecting process; if not, the logic control circuit continues reading the detecting signal until the minimal charging time is reached; and after the minimal charging time is reached, if the detecting signal changes, the logic control circuit sets a detecting abnormal sign to the charging loop detecting, then ends this detecting process; if not, continue with Step C; Step C, the logic control circuit continues reading the detecting signal, and lasts for a predetermined maximal charging time: before the maximal charging time is reached, if the detecting signal changes, the logic control circuit sets a detecting normal sign to the charging loop detecting, then ends this detecting process; if not, the logic control circuit continues reading the detecting signal until the maximal charging time is reached; and after the maximal charging time is reached, if the detecting signal does not change, the logic control circuit sets a detecting abnormal sign to the charging loop detecting, then ends this detecting process; if not, the logic control circuit sets a detecting normal sign to the charging loop detecting, then ends this detecting process. Through the detecting of the charging loop, the logic control circuit becomes able to judge whether or not the connection of the charging control circuit and the storage unit of which the charging loop consists is correct, thus being able to judge whether or not the electronic detonator can realize the storage of ignition energy normally. According to the detecting method above, wherein the detecting of the working state of the safe discharging loop could be carried out in accordance with the following steps: Step A, the logic control circuit sends a control signal to the charging control circuit, rendering it in the non-charging state; the logic control circuit also sends a control signal to the safe discharging circuit, rendering it in the discharging state; Step B, the logic control circuit reads the detecting signal output by the detecting circuit, and lasts for a predetermined maximal discharging time: before the maximal discharging time is reached, if the detecting signal changes, the logic control circuit sets a detecting normal sign to the safe discharging 8 P39337 loop detecting, then ends this detecting process; if not, the logic control circuit continues reading the detecting signal until the maximal discharging time is reached; and after the maximal discharging time is reached, if the detecting signal does not change, the logic control circuit sets a detecting abnormal sign to the safe discharging loop detecting, then ends this detecting process; if not, the logic control circuit sets a detecting normal sign to the safe discharging loop detecting, then ends this detecting process. By detecting the safe discharging loop, the logic control circuit can judge whether or not the connection of the safe discharging circuit and the storage unit of which the safe discharging loop consists is correct, thus being able to judge whether the electronic detonator can safely and normally release the ignition energy when the blast is to be stopped by someone. According to the detecting method mentioned above, the detecting of the working state of the firing loop can be carried out in accordance with the following steps: Step A, the logic control circuit sends a control signal to the charging control circuit, rendering it in the non-charging state; the logic control circuit sends a control signal to the firing control circuit, rendering it in a firing state; Step B, the logic control circuit reads the detecting signal output by the detecting circuit, and lasts for a predetermined maximal discharging time: before the maximal discharging time is reached, if the detecting signal changes, the logic control circuit sets a detecting normal sign to the firing loop detecting, then ends this detecting process; if not, the logic control circuit continues reading the detecting signal until the maximal discharging time is reached; and after the maximal discharging time is reached, if the detecting signal does not change, the logic control circuit sets a detecting abnormal sign to the firing loop detecting, then ends this detecting process; if not, the logic control circuit sets a detecting normal sign to the firing loop detecting, then ends this detecting process. Through the detecting of the firing loop, judging whether the connection of the firing control circuit, the storage unit, and the ignition unit of which the firing loop consists is correct or not is realized, so is judging whether the electronic detonator can quickly release the ignition energy normally when the detonator is to be ignited. According to the detecting method above, wherein Step 4 which realizes the charging to the storage unit can be carried out in accordance with the following steps: Step A, the logic control circuit sends a control signal to the charging control circuit, rendering it in the charging state; the logic control circuit sends control signals to the safe discharging circuit and the firing control circuit respectively to render the safe discharging circuit in the non-discharging state and the firing control circuit in the fire-forbidden state; Step B, the logic control circuit reads the detecting signal output by the detecting circuit: if the detecting signal doesn't change, continue with Step B; if not, end the charging process. The advantages of the aforementioned detecting method lie in: complete 9 P39337 detecting of the working states of the charging loop, the safe discharging loop, and the firing loop of the electronic detonator has been realized in the method. Concretely saying, the detecting of the charging loop realizes the detecting of the function of the charging control circuit, and the capacitance range and the connection state of the ignition capacitor in the storage unit at the external of the chip; the detecting of the safe discharging loop realizes the detecting of the operating performance of the safe discharging circuit and the resistance range of the discharging resistor in the safe discharging circuit; the detecting of the firing loop realizes the detecting of the function of the firing control circuit and the connection state of the ignition unit at the external of the chip. During the process of detecting, the voltage of the connecting end is always not higher than the safe voltage of the ignition unit. What is called the safe voltage is the minimal voltage supplied by the ignition capacitor in the storage unit and needed by the ignition unit to ignite. This ensures that the electronic detonator is always in a safe state during the process of detecting, thus ensuring the security of the use of the electronic detonator. In the detecting method above, the maximal charging time should be longer than the maximal discharging time in the safe discharging loop detecting process, while the maximal discharging time in the safe discharging loop detecting process should be longer than the maximal discharging time in the firing loop detecting process. Brief Description of the Drawings FIG 1 is an integral block diagram of the electronic detonator control chip according to the invention; FIG2 is an embodiment of the detecting circuit whose internal detecting control circuit works with power supply according to the invention; FIG 3 is an embodiment of the detecting circuit whose internal detecting control circuit works without power supply according to the invention; FIG4 is an embodiment of the detecting control circuit working with power supply according to the invention; FIG5 is an embodiment of the detecting control circuit working without power supply according to the invention; FIG6 is another embodiment of the detecting control circuit working without power supply according to the invention; FIG7 is an embodiment of the comparator consisting of resistors and a voltage comparator; FIG8 is an embodiment of the detecting circuit consisting of a Schmitt inverter; FIG9 is an integral flow chart of the detecting method according to the invention; FIG 10 is a flow chart of an embodiment of the charging loop detecting process in the detecting method according to the invention; FIG 11 is a flow chart of an embodiment of the safe discharging loop detecting process in the detecting method according to the invention; 10 P39337 FIG 12 is a flow chart of an embodiment of the firing loop detecting process in the detecting method according to the invention; FIG 13 is a flow chart of an embodiment of the charging process in the detecting method according to the invention; FIG 14 is the waveform of the output voltage of the connecting end in the detecting method according to the invention; FIG 15 is another integral flow chart of the detecting method according to the invention; FIG 16 is a simplified block diagram of the electronic detonator control chip according to the invention; FIG 17 is the formula for calculating the maximal charging time tlma according to the invention; FIG 18 is the formula for calculating the minimal charging time tImin according to the invention; FIG 19 is the formula for calculating the maximal discharging time (t 2 -ti)min in the safe discharging loop detecting process according to the invention; FIG20 is the formula for calculating the maximal discharging time (t4-t 3 )min in the firing loop detecting process according to the invention; and FIG21 is the formula for calculating the predetermined high level voltage V 2 according to the invention. Detailed Description of Embodiments The following further describes the embodiments of the present invention in more details with reference to accompanying drawings. The electronic detonator control chip 100 according to the present invention includes a charging circuit 103, a charging control circuit 110, a power supply management circuit 104, a firing control circuit 105, a logic control circuit 106, a safe discharging circuit 108, and a detecting circuit 111, as illustrated in FIG 16. Wherein the charging control circuit 110 and the safe discharging circuit 108 extend to the exterior of the chip 100 together, forming a connecting end; and the connecting end is further connected with the storage unit 203 and the ignition unit 204 at the external of the chip 100. The detecting circuit 111 starts or stops detecting under the control of a control signal output by the logic control circuit 106, and outputs a detecting signal gained from the connecting end to the logic control circuit 106. The logic control circuit 106 outputs the control signal to the detecting circuit 111 to control the detecting circuit's starting or stopping, reads the detecting signal output by the detecting circuit, and judges whether the circuit connections of the charging control circuit 110, the firing control circuit 105, the safe discharging circuit 108, the storage unit 203, the ignition unit 204, or loops consisted of the combination of the above five components are correct or not according to the detecting signal. The electronic detonator control chip 100 in the present invention is further improved based on the chip disclosed in the Patent ZLO3156912.9 and the Patent ZL200820111269.7. Specifically speaking, the electronic detonator 11 P39337 control chip 100 includes a communication interface circuit 101, a rectifier bridge circuit 102, a charging circuit 103, a charging control circuit 110, a power supply management circuit 104, a firing control circuit 105, a logic control circuit 106, a non-volatile memory 107, a reset circuit 119, a safe discharging circuit 108, a clock circuit 202, and a detecting circuit 111, as illustrated in FIG 1. The detailed connections are described as follows: 1. One end of the charging circuit 103 is connected with the rectifier bridge circuit 102; the other end is connected with the power supply management circuit 104, and the other end also extends to the exterior of the chip 100 to form the pin 1. The charging circuit 103 realizes power storage of the storage unit 203 at the external of the electronic detonator control chip 100. Thus, energy stored in the storage unit 203 can still ensure the electronic detonator control chip 100 to work normally in a certain period of time in case that the power supplied from the external of the electronic detonator is interrupted caused by flying rocks and other accidents in a blasting engineering. 2. One end of the charging control circuit 110 is connected to the rectifier bridge circuit 102; one end is connected to the logic control circuit 106. The other end of the charging control circuit 110 is connected to the safe discharging circuit 108, and this end also extends to the exterior of the chip 100 to form the connecting end 2. The connecting end 2 is used to render the chip 100 charge the ignition capacitor in the storage unit 203; and when it is necessary to cut off this detonation, energy stored in the ignition capacitor will also get into the chip 100 via the connecting end 2 and will be released via the safe discharging circuit 108 that is connected with the connecting end 2 in order to render the electronic detonator get back to a safe state. The charging control circuit 110 realizes the control of the charging process of the ignition capacitor in the storage unit 203 at the external of the electronic detonator control chip 100. Because of the strict control of this charging process, the operation security of the electronic detonator can be assured during preparation for detonation. 3. One end of the safe discharging circuit 108 is connected to the logic control circuit 106, one end is grounded, and another end is connected to the connecting end 2. The safe discharging circuit 108 is used to release the energy stored in the ignition capacitor under the control of the logic control circuit 106. The design of the safe discharging circuit 108 renders the detonation process of the electronic detonator interruptable, thus enhancing the ability of the electronic detonator blasting network in disposing faults. 4. One end of the firing control circuit 105 is grounded, one end extends to the exterior of the chip 100 to form a set of pin 4, and another end is connected with the logic control circuit 106. The firing control circuit 105 interrupts direct connection between the ignition unit 204 and the external detonator wires 201, so that it can protect the ignition unit 204 from the effect of interferences such as static electricity, radio frequency, and stray current, rendering the storage and use of the electronic detonator more secure. The firing control circuit 105 is controlled by the logic control circuit 106, so even if the external storage unit 203 used for enabling the ignition unit 204 and the chip is completely charged to ignite the detonator, the detonator can initiate 12 P39337 only under the control of the specific detonation apparatus at the external of the chip, thus realizing the management of detonation energy, and rendering the detonation process more secure. When it is time to detonate, the firing control circuit 105 will render one end of the ignition unit 204 which is connected to the firing control circuit 105 get grounded under the control of the logic control circuit 106, so that energy stored in the ignition capacitor will be quickly released via the ignition unit 204, with the detonation completed. 5. One end of the logic control circuit 106 is connected to the clock circuit 202, one end is connected with the pin 3, one end is grounded, one end is connected with the non-volatile memory 107, one end is connected with the communication interface circuit 101, one end is connected with the reset circuit 119, one end is connected with the safe discharging circuit 108, one end is connected with the firing control circuit 105. The logic control circuit 106 is the control center of the electronic detonator control chip 100, and controls the working states of circuits of the chip 100, thus realizing the functions such as communication and time delay of the chip 100. 6. One end of the communication interface circuit 101 is grounded, one end extends to the exterior of the chip 100 and is further connected to the detonator wires 201, another end leads to the logic control circuit 106, and another end is connected to the pin 3. The communication interface circuit 101 is used to realize communication between the electronic detonator and the external detonation apparatus, thus realizing bidirectional communication of the electronic detonator blasting network, rendering the electronic detonator programmable online, and also realizing the control of detonation process by the external detonation apparatus, making the detonation process more secure. 7. One end of the rectifier bridge circuit 102 leads to the communication interface circuit 101, and they are connected to the detonator wires 201 at the external of the chip 100 together; another end of the rectifier bridge circuit 102 leads to the charging circuit 103 and the charging control circuit 110, and supplies power to the two circuits; another end of the rectifier bridge circuit 102 is grounded. The existence of the rectifier bridge circuit 102 realizes non-polarity connection of the electronic detonator wires 201 and eliminates the risk of the damage to the electronic detonator control chip 100 caused by reverse connection of the electronic detonator wires 201, rendering the detonation process easier and more secure. 8. One end of the power supply management circuit 104 is connected to the pin 1, one end is grounded, and another end extends to the exterior of the chip 100, forming a set of pin 3 which acts as a power supply output terminal. The power supply management circuit 104 supplies operating power to the components inside the chip 100, and the power supply output terminal also extends to the exterior of the chip 100, forming the pin 3. If the electronic detonator demands higher delay precision, the pin 3 extending to the exterior of the chip 100 can be connected to the positive pole of a capacitor, with the negative pole of the capacitor being grounded, thus forming a decoupling circuit that can filter out noises of the operating power supply caused by the chip 100, improving the delay precision of the electronic detonator. 9. One end of the non-volatile memory 107 is connected to the pin 3, one end is connected with the logic control circuit 106, and another end is 13 P39337 grounded. The non-volatile memory 107 is adopted to store the information of electronic coding and identity serial number of the electronic detonator in order to realize the identity/password management of the electronic detonators, avoiding coding and tagging in the process of detonator manufacturing, thus improving production security of the detonators. 10. One end of the reset circuit 119 is grounded, one end is connected to the pin 3, and another end is connected to the logic control circuit 106. The reset circuit 119 is used to provide initial states for the chip 100 in order to avoid logic confusion within the chip. 11. One end of the clock circuit 202 is connected to the pin 3, the other end leads to the logic control circuit 106. The clock circuit 202 makes the delay time of the detonator more accurate. 12. The power supply input terminal 30 of the detecting circuit 111 is connected to the pin 3 and the output terminal of the power supply management circuit 104 within the chip 100. Another end of the detecting circuit 111 is connected with the logic control circuit 106 to receive the control signal sent by the logic control circuit 106, and to output the detecting signal of the detecting circuit 111 to the logic control circuit 106. The detecting signal input terminal 31 of the detecting circuit 111 is connected with the charging control circuit 110 and the safe discharging circuit 108, and is connected to the connecting end 2 within the chip 100. And another end of the detecting circuit 111 is grounded. The pin 1 is connected to one end of the storage unit 203 at the external of the chip 100, the other end of the storage unit 203 is connected with the connecting end 2 and one end of the ignition unit 204 at the external of the chip 100 jointly, while the other end of the ignition unit 204 is connected to the pin 4. During the detecting process, the voltage of the ignition capacitor in the storage unit 203 is output to the detecting signal input terminal 31 of the detecting circuit 111 via the connecting end 2. As an embodiment of the present invention shown in FIG2, the detecting circuit 111 includes a detecting control circuit 200, a comparator 202, and a PMOS transistor 231. The power supply input terminal 263 of the detecting control circuit 200, and the source and the substrate of the PMOS transistor 231 connect together, and are connected to the pin 3 jointly, forming the power supply input terminal 30 of the detecting circuit 111, being powered by the power supply management circuit 104. The control terminal 260 of the detecting control circuit 200 is connected to the logic control circuit 106 to receive the control signal sent by the logic control circuit 106. The input terminal 261 of the detecting control circuit 200 is connected to the safe discharging circuit 108 and the charging control circuit 110, and they are connected to the connecting end 2 jointly, forming the detecting signal input terminal 31 of the detecting circuit 111. The output terminal 262 of the detecting control circuit 200 is connected to the signal input terminal 271 of the comparator 202; another terminal of the detecting control circuit 200 is grounded. The grid of the PMOS transistor 231 is connected to the logic control circuit 106, and its drain is connected to the power supply input terminal 270 of the comparator 202. The signal output terminal 272 of the comparator 202 leads to the logic control circuit 106, forming the detecting signal output terminal of the detecting circuit 111, and the other end of the 14 P39337 comparator 202 is grounded. As another embodiment of the present invention shown in FIG3, the detecting circuit 111 includes a detecting control circuit 300, a comparator 202, and a PMOS transistor 231. The control terminal 260 of the detecting control circuit 300 is connected to the logic control circuit 106 to receive the control signal sent by the logic control circuit 106. The input terminal 261 of the detecting control circuit 300 is connected to the safe discharging circuit 108 and the charging control circuit 110, and they are connected to the connecting end 2 jointly, forming the detecting signal input terminal 31 of the detecting circuit 111. The output terminal 262 of the detecting control circuit 300 is connected to the signal input terminal 271 of the comparator 202, and another end of the detecting control circuit 300 is grounded. The source and the substrate of the PMOS transistor 231 are connected to the pin 3, forming the power supply input terminal 30 of the detecting circuit 111, being powered by the power supply management circuit 104. The grid of the PMOS transistor 231 is connected to the logic control circuit 106, and its drain is connected to the power supply input terminal 270 of the comparator 202. The signal output terminal 272 of the comparator 202 leads to the logic control circuit 106, forming the detecting signal output terminal of the detecting circuit 111, and the other end of the comparator 202 is grounded. In the embodiments illustrated in FIG2 and FIG3, the detecting control circuit 200 or the detecting control circuit 300 controls the signal input from the connecting end 2 according to the signal output by the logic control circuit 106. The comparator 202 transforms the detecting signal obtained from the connecting end 2 to a logic signal that the logic control circuit 106 can identify, and outputs the logic signal to the logic control circuit 106. The PMOS transistor 231 is adopted to control the power supplied to the comparator 202 according to the signal output by the logic control circuit 106, reducing the power consumption of the detecting circuit 11I in the non-working state. As illustrated in FIG4, the detecting control circuit 200 includes a resistor 211, a resistor 212, a PMOS transistor 232, a PMOS transistor 233, a PMOS transistor 234, an NMOS transistor 241, an NMOS transistor 242, and an NMOS transistor 243. Wherein the source and the substrate of the PMOS transistor 232 are connected to the pin 3, being powered by the power supply management circuit 104; the grid of the PMOS transistor 232 is connected to the logic control circuit 106, and is connected to the grid of the NMOS transistor 241 and the grid of the NMOS transistor 243 jointly; the drain of the PMOS transistor 232 is connected to the drain of the NMOS transistor 241 and the grid of the NMOS transistor 242. The source and the substrate of the PMOS transistor 233, the source and the substrate of the PMOS transistor 234 are connected to the safe discharging circuit 108 and the charging control circuit 110 together, and are connected to the connecting end 2, forming the input terminal of the detecting control circuit 200; the drain of the PMOS transistor 233 is connected with the drain of the NMOS transistor 242 and the grid of the PMOS transistor 234; the grid of the PMOS transistor 233 is connected to the drain of the PMOS transistor 234 and the drain of the NMOS transistor 243, and they are connected to one end of the resistor 211 jointly. The source and the substrate of the NMOS transistor 241, the source and the substrate of the NMOS transistor 242, and the source and the substrate of the 15 P39337 NMOS transistor 243 are grounded. One end of the resistor 211 is connected to the grid of the PMOS transistor 233, the drain of the PMOS transistor 234, and the drain of the NMOS transistor 243 jointly; the other end of the resistor 211 is connected to the signal input terminal 271 of the comparator 202, forming the output terminal of the detecting control circuit 200, and this end is also grounded via the resistor 212. As shown in FIG5, the detecting control circuit 300 includes a PMOS transistor 235, an NMOS transistor 244, a resistor 211, a resistor 212, and a resistor 213. The source and the substrate of the PMOS transistor 235 are connected to one end of the resistor 213, and they are jointly connected to the safe discharging circuit 108 and the charging control circuit 110; and this end of the resistor 213 also leads to the connecting end 2, forming the input terminal of the detecting control circuit 300; the drain of the PMOS transistor 235 is connected to one end of the resistor 211; the grid of the PMOS transistor 235 is connected to the other end of the resistor 213, and they are connected to the drain of the NMOS transistor 244 jointly. The source and the substrate of the NMOS transistor 244 are grounded, its grid is connected with the logic control circuit 106, and its drain is connected with the grid of the PMOS transistor 235. One end of the resistor 212 is grounded; the other end of the resistor 212 is connected to the other end of the resistor 211, and they are jointly connected to the signal input terminal 271 of the comparator 202, forming the output terminal of the detecting control circuit 300. As illustrated in FIG6, the detecting control circuit 300 includes a resistor 211, a resistor 212, and an NMOS transistor 245. Wherein the source and the substrate of the NMOS transistor 245 are grounded, its grid is connected with the logic control circuit 106, and its drain is connected with one end of the resistor 212. The other end of the resistor 212 is connected with one end of the resistor 211, and they lead to the signal input terminal 271 of the comparator 202 together, forming the output terminal of the detecting control circuit 300. The other end of the resistor 211 is connected to the safe discharging circuit 108 and the charging control circuit 110, and this end also leads to the connecting end 2, forming the input terminal of the detecting control circuit 300. In this embodiment, the signal input to the detecting circuit 111 directly acts on the signal input terminal 271 of the comparator 202, so the signal input terminal 271 of the comparator 202 adopted in this embodiment can endure voltage at high level. Before the detecting process indicated in FIG 9 or FIG 15 starts, the logic control circuit 106 sends a logic control signal with high level to the detecting control circuit 200 or the detecting control circuit 300 illustrated in FIG4, FIG5 or FIG 6, to make the detecting circuit 111 get into the working state. The voltage of the ignition capacitor in the storage unit 203 going through the connecting end 2 is divided by the detecting control circuit 200 or the detecting control circuit 300, and then the divided voltage acts on the signal input terminal 271 of the comparator 202. After the detecting process indicated in FIG9 ends, the logic control circuit 106 will send a logic control signal with low level to the detecting control circuit 200 or the detecting control circuit 300 to stop the detecting circuit 111, thus avoiding leakage current caused by the resistor 211 and the resistor 212 which divide the voltage. 16 P39337 As shown in FIG7, the comparator 202 mentioned above includes a voltage comparator 220, a resistor 214, a resistor 215, and a resistor 216. Wherein the resistor 214 is connected between the in-phase input terminal 282 and the power supply input terminal 280 of the voltage comparator 220, and they are connected to the drain of the PMOS transistor 231 jointly. The resistor 215 is connected between the in-phase input terminal 282 of the voltage comparator 220 and the ground, and the resistor 216 crosses over the in-phase input terminal 282 and the output terminal 283 of the voltage comparator 220. The out-phase input terminal 281 of the voltage comparator 220 is connected to the output terminal 262 of the detecting control circuit 200, forming the signal input terminal 271 of the comparator 202; the output terminal 283 of the voltage comparator 220 leads to the logic control circuit 106, forming the signal output terminal 272 of the comparator, and the other terminal of the voltage comparator 220 is grounded. As illustrated in FIG 8, the detecting circuit 111 is a Schmitt inverter 158. The power supply input terminal of the Schmitt inverter 158 is connected with the pin 3 and the power supply management circuit 104, forming the power supply input terminal of the detecting circuit 111. The input terminal of the Schmitt inverter 158 is connected to the charging control circuit 110, the safe discharging circuit 108, and the connecting end 2, forming the detecting signal input terminal of the detecting circuit 111. The output terminal of the Schmitt inverter 158 leads to the logic control circuit 106, forming the detecting signal output terminal of the detecting circuit 111. And the other terminal of the Schmitt inverter 158 is grounded. As indicated in FIG9, the method provided in this invention to detect the electronic detonator control chip 100 can be carried out in accordance with the following steps, with reference to FIG 16 or FIG 1: Step 1, the logic control circuit 106 detects the default initial working states of the charging control circuit 110, the safe discharging circuit 108, and the firing control circuit 105: if any one of the default initial working states is abnormal, continue with Step 6; if all the default initial working states are normal, continue with Step 2; Step 2, detect the working state of the charging loop composed of the charging control circuit 110 and the storage unit 203: if the working state of the charging loop is detected to be normal, continue with Step 3; if not, continue with Step 6; Step 3, detect the working state of the firing loop composed of the storage unit 203, the ignition unit 204, and the firing control circuit 105: if the working state of the firing loop is detected to be normal, continue with Step 4; if not, continue with Step 6; Step 4, charge the storage unit 203 at the external of the chip 100 to the predetermined high level voltage; Step 5, detect the safe discharging loop composed of the storage unit 203 and the safe discharging circuit 108, save the detecting result, and then continue with Step 6; Step 6, the logic control circuit 106 sends control signals to the charging control circuit 110, the safe discharging circuit 108, and the firing control 17 P39337 circuit 105 respectively to make them return to their respective default initial working state; then end this detecting method. The default initial working states mentioned above are normal when the charging control circuit 110 is in the non-charging state, the safe discharging circuit 108 is in the discharging state, and the firing control circuit 105 is in the fire-forbidden state. The default initial working states mentioned above can be detected by detecting the voltage of the connecting end 2, that is: if the voltage of the connecting end 2 is higher than the predetermined high level voltage, the logic control circuit 106 will judge that the default initial working states are abnormal, then continue with Step 6 directly; if the voltage of the connecting end 2 is not higher than the predetermined high level voltage, continue with Step 2. The sequence of the firing loop detecting and the safe discharging loop detecting shown in FIG9 can be interchanged, as indicated in FIG 15, and the detecting flows illustrated in FIG9 and FIG 15 are equivalent. As shown in FIG 10, detecting of the working state of the charging loop in Step 2 in the aforementioned detecting method can be carried out in accordance with the following steps, with reference to FIG 16 or FIG 1: Step A, the logic control circuit 106 sends a control signal to the safe discharging circuit 108, rendering it in the non-discharging state; the logic control circuit 106 also sends a control signal to the charging control circuit 110, rendering it in the charging state; Step B, the logic control circuit 106 reads the detecting signal output by the detecting circuit 111, and lasts for a minimal charging time that is predetermined: before the minimal charging time is reached, if the detecting signal changes, the logic control circuit 106 sets a detecting abnormal sign to the charging loop detecting, then end this detecting process; if not, the logic control circuit 106 continues reading the detecting signal until the minimal charging time is reached; when and after the minimal charging time is reached, if the detecting signal changes, the logic control circuit 106 sets a detecting abnormal sign to the charging loop detecting, then end this detecting process; if not, continue with Step C; Step C, the logic control circuit 106 continues reading the detecting signal output by the detecting circuit 111, and lasts for a maximal charging time that is predetermined: before the maximal charging time is reached, if the detecting signal changes, the logic control circuit 106 sets a detecting normal sign to the charging loop detecting, then end this detecting process; if not, the logic control circuit 106 continues reading the detecting signal until the maximal charging time is reached; when and after the maximal charging time is reached, if the detecting signal does not change, the logic control circuit 106 sets a detecting abnormal sign to the charging loop detecting, then end this detecting process; if not, the logic control circuit 106 sets a detecting normal sign to the charging loop detecting, then end this detecting process. As shown in FIG 13, the charging process of the storage unit 203 in Step 4 in the detecting method mentioned above can be carried out in accordance with the following steps, with reference to FIG 16 and FIG 1: 18 P39337 Step A, the logic control circuit 106 sends a control signal to the charging control circuit 110, rendering it in the charging state; the logic control circuit 106 sends control signals to the safe discharging circuit 108 and the firing control circuit 105 respectively to make the safe discharging circuit 108 in the non-discharging state and to make the firing control circuit 105 in the fire-forbidden state; Step B, the logic control circuit 106 reads the detecting signal output by the detecting circuit 111: if the detecting signal doesn't change, continue with Step B; if not, end the charging process. As shown in FIG 11, detecting of the safe discharging loop in the detecting method mention above can be carried out in accordance with the following steps, with reference to FIG 16 and FIG 1: Step A, the logic control circuit 106 sends a control signal to the charging control circuit 110, rendering it in the non-charging state; the logic control circuit 106 also sends a control signal to the safe discharging circuit 108, rendering it in the discharging state; Step B, the logic control circuit 106 reads the detecting signal output by the detecting circuit 111, and lasts for a maximal discharging time that is predetermined: before the maximal discharging time is reached, if the detecting signal changes, the logic control circuit 106 sets a detecting normal sign to the safe discharging loop detecting, then ends this detecting process; if not, the logic control circuit 106 continues reading the detecting signal until the maximal discharging time is reached; when and after the maximal discharging time is reached, if the detecting signal does not change, the logic control circuit 106 sets a detecting abnormal sign to the safe discharging loop detecting, then end this detecting process; if not, the logic control circuit 106 sets a detecting normal sign to the safe discharging loop detecting, then end this detecting process. As shown in FIG 12, detecting of the firing loop in the aforementioned detecting method can be carried out in accordance with the following steps, with reference to FIG 16 and FIG 1: Step A, the logic control circuit 106 sends a control signal to the charging control circuit 110, rendering it in the non-charging state; the logic control circuit 106 also sends a control signal to the firing control circuit 105, rendering it in the firing state; Step B, the logic control circuit 106 reads the detecting signal output by the detecting circuit 111, and lasts for a maximal discharging time that is predetermined: before the maximal discharging time is reached, if the detecting signal changes, the logic control circuit 106 sets a detecting normal sign to the firing loop detecting, then end this detecting process; if not, the logic control circuit 106 continues reading the detecting signal until the maximal discharging time is reached; when and after the maximal discharging time is reached, if the detecting signal does not change, the logic control circuit 106 sets a detecting abnormal sign to the firing loop detecting, then end this detecting process; if not, the logic control circuit 106 sets a detecting normal sign to the firing loop detecting, then end this detecting process. In the process mentioned above, with reference to FIG 16 and FIG 1, the 19 P39337 voltage of the connecting end 2 is always not higher than the voltage of the ignition capacitor in the storage unit 203 which is one part of the firing loop consisted of the storage unit 203, the ignition unit 204 and the firing control circuit 105, ensuring that the energy stored in the storage unit 203 can not ignite the ignition unit 204, thus ensuring the security of the detecting process. That is, during the detecting process mentioned above, the voltage of the connecting end 2 is always not higher than the safe voltage of the ignition unit 204 that is the minimal voltage supplied by the ignition capacitor in the storage unit 203 and needed by the ignition unit 204 to ignite. In the detecting method mentioned above, detecting of the initial working states can ensure that the voltage of the ignition capacitor is lower than the safe voltage, thus ensuring the security of the detecting process and the veracity of the function of charging-forbidden of the charging control circuit. The maximal charging time is longer than the maximal discharging time in the safe discharging loop detecting process, and the maximal discharging time in the safe discharging loop detecting process is longer than the maximal discharging time in the firing loop detecting process. Take the detecting process shown in FIG 15 as an example to describe the process of the detecting method accompany with FIG 14 which shows the waveform of the output voltage of the connecting end 2. During this process, it is demanded that: (1) the charging time ti of the charging loop is between the minimal charging time and the maximal charging time; (2) the discharging time (t 2 -ti) in the safe discharging loop detecting is no longer than the maximal discharging time in the detecting of the safe discharging loop; (3) the ignition time (t 4 -t 3 ) is no longer than the maximal discharging time in the detecting of the firing loop. The symbols V 2 and V, respectively stand for the threshold voltage with high level and the threshold voltage with low level of the detecting signal input terminal 31 of the detecting circuit 111. The charging time and the discharging time of the ignition capacitor in the storage unit 203 at the external of the chip 100 depend on the capacitance of the ignition capacitor and the resistance of each detecting loop in the detecting process. Phase I shown in FIG 14 is the charging loop detecting phase. The maximal charging time tl,max of the charging loop detecting process can be calculated according to the formula shown in FIG 17. Wherein the symbol Cmax stands for the maximal capacitance of the ignition capacitor in the external storage unit 203; the symbol R, stands for the equivalent resistance of the charging loop; the symbol V 2 stands for the input threshold voltage at high level of the detecting circuit 111; and the symbol V stands for the charging input voltage. In the condition that the equivalent resistance R, and the charging input voltage V are determined, if the charging time is longer than the maximal charging time ti,max which means the charging loop is detected to be abnormal, the judgment can be: the charging control circuit 110 can't realize the function of charging, the fire-forbidden state of the firing control circuit 105 is invalidated, the non-discharging state of the safe discharging circuit 108 is invalidated, or the external capacitance of the storage unit 203 is beyond the maximal allowable capacitance, for example, the equivalent capacitance is 20 P39337 infinite due to shorted capacitor or some other faults. The minimal charging time ti,min is calculated by the formula shown in FIG 18. Wherein the symbol Cmin stands for the minimal allowable capacitance of the ignition capacitor in the external storage unit 203; the symbol Ri stands for the equivalent resistance of the charging loop; the symbol V 2 stands for the input threshold voltage with high level of the detecting circuit 111; and the symbol V stands for the charging input voltage. In the condition that the equivalent resistance R, and the charging input voltage V are determined, if the charging time is shorter than the minimal charging time ti,min which means the charging loop is detected to be abnormal, the judgment can be: the function of charging of the charging control circuit 110 is abnormal, the function of fire-forbidden of the firing control circuit 105 is abnormal, the function of non-discharging of the safe discharging circuit 108 is abnormal, or the capacitance of the ignition capacitor is less than the capacitance that the ignition unit 204 needs to ignite reliably (for example, faults such as faulty connection at the exterior of the ignition capacitor or weak weld that make the capacitor open-circuited will also result in smaller equivalent capacitance). To sum up, in the condition that the equivalent resistance R, and the charging input voltage V are determined, detecting the time range of the charging process can realize the detecting of the capacitance range and the connection state of the ignition capacitor, the charging function of the charging control circuit, the discharge-forbidden function of the safe discharging circuit, and the fire-forbidden function of the firing control circuit as well. Phase Il shown in FIG 14 is the safe discharging loop detecting phase. The maximal discharging time (t 2 -ti)min of the safe discharging loop detecting process can be calculated according to the formula shown in FIG 19. Wherein the symbol R 2 ,max stands for the maximal allowable resistance of the equivalent resistor of the safe discharging loop; the symbol C stands for the capacitance of the ignition capacitor in the external storage unit 203; the symbol V 2 stands for the input threshold voltage at high level of the detecting circuit 111; and the symbol V, stands for the input threshold voltage at low level of the detecting circuit 111. The purpose of detecting the maximal discharging time (t 2 -ti)min of the safe discharging loop is to control the speed of response to faulty states of the safe discharging circuit. If the safe discharging loop is detected to be normal, on the one hand, veracity of the discharging function of the safe discharging circuit can be assured; on the other hand, the equivalent resistance of the safe discharging loop can be assured to be in the allowable range around its default. Phase IV shown in FIG 14 is the firing loop detecting phase. The maximal discharging time (t 4 t 3 )min of the firing loop detecting process can be calculated according to the formula shown in FIG20. Wherein the symbol R 3 ,max stands for the maximal allowable resistance of the equivalent resistor of the firing loop; the symbol C stands for the capacitance of the ignition capacitor in the external storage unit 203; the symbol V 2 stands for the input threshold voltage at high level of the detecting circuit 111; and the symbol V 1 stands for the input threshold voltage at low level of the detecting circuit 111. 21 P39337 If the firing loop is detected to be normal, on the one hand, veracity of the firing function of the firing control circuit can be assured; on the other hand, the equivalent resistance of the firing loop can be assured to be no larger than the maximal allowable resistance R3,max, which means the connection of the external ignition unit is reliable. Phase II shown in FIG 14 is the charging phase in which the storage unit 203 is charged between the safe discharging loop detecting and the firing loop detecting. To ensure the security of the detecting process, the predetermined high level voltage V 2 in the charging phase can be calculated according to the energy stored in the ignition capacitor, as shown in the formula illustrated in FIG21. It is demanded that the value of the energy is far less than the ignition energy of the ignition unit. To sum up, the present invention provides a detecting circuit and its detecting method, realizing the complete detecting of the working process including charging, firing, and safe discharging of the electronic detonator. In the present detecting method, working loops of the electronic detonator are adopted as detecting loops which are exactly the same as the loops when the electronic detonator works, realizing real and reliable detecting of various working loops, thus ensuring veracity of the electronic detonator control chip. 22 P39337

Claims

1. An electronic detonator control chip, including a charging circuit, a charging control circuit, a power supply management circuit, a firing control circuit, a logic control circuit, and a safe discharging circuit, and in which the charging control circuit and the safe discharging circuit extend to the exterior of the chip together, forming a connecting end which is further connected to a storage unit and an ignition unit at the external of the chip, and characterized in that: the chip further includes a detecting circuit; the detecting circuit starts or stops detecting under the control of a control signal output by the logic control circuit, and outputs a detecting signal gained from the connecting end to the logic control circuit; and the logic control circuit outputs the control signal to the detecting circuit to control its starting or stopping, reads the detecting signal output by the detecting circuit, and judges whether or not the circuit connections of the charging control circuit, the firing control circuit, the safe discharging circuit, the storage unit, the ignition unit, or loops consisted of the combination of the above five components are correct according to the detecting signal.

2. The electronic detonator control chip according to claim 1, characterized in that the chip further includes a communication interface circuit, a rectifier bridge circuit, a non-volatile memory, a reset circuit, and a clock circuit; a first end of the charging circuit is connected with the rectifier bridge circuit; a second end of the charging circuit is connected to the power supply management circuit, and the second end also extends to the exterior of the chip to form a set of first pin; a first end of the charging control circuit is connected to the rectifier bridge circuit, a second end of the charging control circuit is connected to the logic control circuit; a third end of the charging control circuit is connected to the safe discharging circuit, and the third end also extends to the exterior of the chip to form the connecting end; a first end of the safe discharging circuit is connected to the logic control circuit, a second end of the safe discharging circuit is grounded, and a third end of the safe discharging circuit is connected to the connecting end; a first end of the power supply management circuit is connected to the first pin, a second end of the power supply management circuit is grounded, and a third end of the power supply management circuit extends to the exterior of the chip, forming a set of third pin which acts as a power supply output terminal; a first of the firing control circuit is grounded; a second end of the firing 23 P39337 control circuit extends to the exterior of the chip, forming a set of fourth pin; and a third end of the firing control circuit is connected to the logic control circuit; and a first end of the logic control circuit is connected to the clock circuit, a second end of the logic control circuit is connected with the third pin, a third end of the logic control circuit is grounded, a fourth end of the logic control circuit is connected with the non-volatile memory, a fifth end of the logic control circuit is connected with the communication interface circuit, a sixth end of the logic control circuit is connected with the reset circuit, a seventh end of the logic control circuit is connected with the safe discharging circuit, a eighth end of the logic control circuit is connected with the firing control circuit, and a ninth end of the logic control circuit is connected with the charging control circuit.

3. The electronic detonator control chip according to claim 1 or 2, characterized in that a power supply input terminal of the detecting circuit is connected to the power supply output terminal of the power supply management circuit, being powered by the power supply management circuit; a detecting signal input terminal of the detecting circuit is connected to the charging control circuit and the safe discharging circuit, and is connected to the connecting end within the chip; another end of the detecting circuit is grounded; and another end of the detecting circuit is connected to the logic control circuit.

4. The electronic detonator control chip according to claim 3, characterized in that the detecting circuit is a Schmitt inverter.

5. The electronic detonator control chip according to claim 3, characterized in that the detecting circuit includes a detecting control circuit, a comparator, and a first PMOS transistor; a power supply input terminal of the detecting control is connected with the source and the substrate of the first PMOS transistor, and the power supply input terminal of the detecting control and the source and the substrate of the first PMOS transistor are all connected to the third pin, forming the power supply input terminal of the detecting circuit, being powered by the power supply management circuit; a control terminal of the detecting control circuit is connected to the logic control circuit, receiving the control signal sent by the logic control circuit; a terminal of the detecting control circuit is connected to the safe discharging circuit and the charging control circuit, and they are jointly connected to the connecting end, forming the detecting signal input terminal of the detecting circuit; an output terminal of the detecting control circuit is connected to the signal input terminal of the comparator; another terminal of the detecting control circuit is grounded; 24 P39337 the grid of the first PMOS transistor is connected to the logic control circuit, and its drain is connected to the power supply input terminal of the comparator; and the signal output terminal of the comparator leads to the logic control circuit, forming the detecting signal output terminal of the detecting circuit, and the other end of the comparator is grounded.

6. The electronic detonator control chip according to claim 5, characterized in that the detecting control circuit includes a first resistor, a second resistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a first NMOS transistor, a second NMOS transistor, and a third NMOS transistor, the source and the substrate of the second PMOS transistor are connected to the third pin, powered by the power supply management circuit; the grid of the second PMOS transistor is connected to the logic control circuit, and is jointly connected to the grid of the first NMOS transistor and the grid of the third NMOS transistor; the drain of the second PMOS transistor is connected to the drain of the first NMOS transistor and the grid of the second NMOS transistor; the source and the substrate of the third PMOS transistor, the source and the substrate of the fourth PMOS transistor are jointly connected to the safe discharging circuit and the charging control circuit, and are connected to the connecting end, forming the input terminal of the detecting control circuit; the drain of the third PMOS transistor is connected to the drain of the second NMOS transistor and the grid of the fourth PMOS transistor; the grid of the third PMOS transistor is connected to the drain of the fourth PMOS transistor and the drain of the third NMOS transistor, and they are connected to one end of the first resistor together; the source and the substrate of the first NMOS transistor, the source and the substrate of the second NMOS transistor, and the source and the substrate of the third NMOS transistor are all grounded; and a first end of the first resistor is jointly connected to the grid of the third PMOS transistor, the drain of the fourth PMOS transistor, and the drain of the third NMOS transistor; a second end of the first resistor is connected to the signal input terminal of the comparator, forming the output terminal of the detecting control circuit, and the second end is grounded via the second resistor.

7. The electronic detonator control chip according to claim 3, characterized in that the detecting circuit includes a detecting control circuit, a comparator, and a first PMOS transistor; the control terminal of the detecting control circuit is connected to the logic control circuit to receive the control signal sent by the logic control circuit; the input terminal of the detecting control circuit is jointly connected to 25 P39337 the safe discharging circuit and the charging control circuit, and is also connected to the connecting end, forming the detecting signal input terminal of the detecting circuit; the output terminal of the detecting control circuit is connected to the signal input terminal of the comparator; another terminal of the detecting control circuit is grounded; the source and the substrate of the first PMOS transistor are connected to the third pin, forming the power supply input terminal of the detecting circuit, powered by the power supply management circuit; the grid of the first PMOS transistor is connected to the logic control circuit, and the drain of the first PMOS transistor is connected to the power supply input terminal of the comparator; and the signal output terminal of the comparator leads to the logic control circuit, forming the detecting signal output terminal of the detecting circuit, and the other end of the comparator is grounded.

8. The electronic detonator control chip according to claim 7, characterized in that the detecting control circuit includes a fifth PMOS transistor, a fourth NMOS transistor, a first resistor, a second resistor, and a third resistor; the source and the substrate of the fifth PMOS transistor are connected to one end of the third resistor, and they are also connected to the safe discharging circuit and the charging control circuit; the end of the third resistor also leads to the connecting end, forming the input terminal of the detecting control circuit; the drain of the fifth PMOS transistor is connected to a first end of the first resistor; the grid of the fifth PMOS transistor is connected to the other end of the third resistor, and they are jointly connected to the drain of the fourth NMOS transistor; the source and the substrate of the fourth NMOS transistor are grounded, its grid is connected with the logic control circuit, and its drain is connected with the grid of the fifth PMOS transistor; and a first end of the second resistor is grounded; a second end of the second resistor is connected to a second of the first resistor, and they are both connected to the signal input terminal of the comparator, forming the output terminal of the detecting control circuit.

9. The electronic detonator control chip according to claim 7, characterized in that the detecting control circuit includes a first resistor, a second resistor, and a fifth NMOS transistor; the source and the substrate of the fifth NMOS transistor are grounded, its grid is connected with the logic control circuit, and its drain is connected with one end of the second resistor; the other end of the second resistor is connected with one end of the first resistor, and they jointly lead to the signal input terminal of the comparator, 26 P39337 forming the output terminal of the detecting control circuit; and the other end of the first resistor is connected to the safe discharging circuit and the charging control circuit, and the other end also leads to the connecting end, forming the input terminal of the detecting control circuit.

10. The electronic detonator control chip according to claim 5 or claim 7, characterized in that the comparator includes a voltage comparator, a fourth resistor, a fifth resistor, and a sixth resistor; the fourth resistor is connected between the in-phase input terminal and the power supply input terminal of the voltage comparator, and they are connected to the drain of the first PMOS transistor jointly; the fifth resistor is connected between the in-phase input terminal of the voltage comparator and the ground, and the sixth resistor crosses over the in-phase input terminal and the output terminal of the voltage comparator; and the out-phase input terminal of the voltage comparator is connected to the output terminal of the detecting control circuit, forming the signal input terminal of the comparator; the output terminal of the voltage comparator leads to the logic control circuit, forming the signal output terminal of the comparator, and the other terminal of the voltage comparator is grounded.

11. A method of detecting the connection correctness of the electronic detonator control chip, characterized in that the method is carried out in accordance with the following steps: Step 1, detecting the default initial working states of the charging control circuit, the safe discharging circuit, and the firing control circuit: if any one of the default initial working states is abnormal, Step 6 is executed; if all the default initial working states are normal, Step 2 is executed; the Step 2, detecting the working state of the charging loop composed of the charging control circuit and the storage unit: if the working state of the charging loop is detected to be normal, Step 3 is executed; if not, the Step 6 is executed; the Step 3, detecting the working state of one of the following two loops, which are the firing loop composed of the storage unit, the ignition unit, and the firing control circuit, and the safe discharging loop composed of the storage unit and the safe discharging circuit: if the working state of the loop detected is normal, Step 4 is executed; if not, the Step 6 is executed; the Step 4, charging the storage unit to a predetermined high level voltage; Step 5, detecting the other loop that has not been detected between the safe discharging loop and the firing loop mentioned in Step 3; Step 6, sending control signals to the charging control circuit, the safe discharging circuit, and the firing control circuit respectively, rendering them back to their respective default initial working state; then ending the detecting method. 27 P39337

12. The detecting method according to claim 11, characterized in that the default initial working states in the Step 1 are normal when the charging control circuit is in a non-charging state, the safe discharging circuit is in a discharging state, and the firing control circuit is in a fire-forbidden state.

13. The detecting method according to claim 11, characterized in that the Step 1, the detecting of the default initial working states, is carried out by detecting the voltage of the connecting end: if the voltage of the connecting end is higher than the predetermined high level voltage, the logic control circuit will judge that the default initial working states are abnormal; if not, the logic control circuit will judge that the default initial working states are normal.

14. The detecting method according to claim 11, characterized in that the Step 2, the detecting of the working state of the charging loop, is carried out in accordance with the following steps, Step A, the logic control circuit sending a control signal to the safe discharging circuit, rendering it in a non-discharging state; the logic control circuit sending a control signal to the charging control circuit, rendering it in a charging state; Step B, the logic control circuit reading the detecting signal from the detecting signal output terminal, and lasting for a minimal charging time that is predetermined: before the minimal charging time is reached, if the detecting signal changes, the logic control circuit setting a detecting abnormal sign to the charging loop detecting, then ending the detecting process; if not, continuing reading the detecting signal until the minimal charging time is reached; and when and after the minimal charging time is reached, if the detecting signal changes, the logic control circuit setting a detecting abnormal sign to the charging loop detecting, then ending the detecting process; if not, Step C is executed; the Step C, the logic control circuit continuing reading the detecting signal, and lasting for a maximal charging time that is predetermined: before the maximal charging time is reached, if the detecting signal changes, the logic control circuit setting a detecting normal sign to the charging loop detecting, then ending the detecting process; if not, the logic control circuit continuing reading the detecting signal until the maximal charging time is reached; and when and after the maximal charging time is reached, if the detecting signal does not change, the logic control circuit setting a detecting abnormal sign to the charging loop detecting, then ending the detecting process; if not, the logic control circuit setting a detecting normal sign to the charging loop detecting, then ending 28 P39337 the detecting process.

15. The detecting method according to claim 11, characterized in that the detecting of the working state of the safe discharging loop is carried out in accordance with the following steps: Step A, the logic control circuit sending a control signal to the charging control circuit, rendering it in the non-charging state; the logic control circuit sending a control signal to the safe discharging circuit, rendering it in the discharging state; Step B, the logic control circuit reading the detecting signal output by the detecting circuit, and lasting for a maximal discharging time that is predetermined: before the maximal discharging time is reached, if the detecting signal changes, the logic control circuit setting a detecting normal sign to the safe discharging loop detecting, then ending the detecting process; if not, continuing reading the detecting signal until the maximal discharging time is reached; and when and after the maximal discharging time is reached, if the detecting signal does not change, the logic control circuit setting a detecting abnormal sign to the safe discharging loop detecting, then ending the detecting process; if not, the logic control circuit setting a detecting normal sign to the safe discharging loop detecting, then ending the detecting process.

16. The detecting method according to claim 11, characterized in that the detecting of the working state of the firing loop is carried out in accordance with the following steps: Step A, the logic control circuit sending a control signal to the charging control circuit, rendering it in the non-charging state; the logic control circuit sending a control signal to the firing control circuit, rendering it in the firing state; Step B, the logic control circuit reading the detecting signal output by the detecting circuit, and lasting for a maximal discharging time that is predetermined: before the maximal discharging time is reached, if the detecting signal changes, the logic control circuit setting a detecting normal sign to the firing loop detecting, then ending the detecting process; if not, continuing reading the detecting signal until the maximal discharging time is reached; and when and after the maximal discharging time is reached, if the detecting signal does not change, the logic control circuit setting a detecting abnormal sign to the firing loop detecting, then ending the detecting process; if not, the logic control circuit setting a detecting normal sign to the firing loop detecting, then ending the detecting process. 29 P39337

17. The detecting method according to claim 11, characterized in that Step 4 is carried out in accordance with the following steps: Step A, the logic control circuit sending a control signal to the charging control circuit, rendering it in the charging state; the logic control circuit sending control signals to the safe discharging circuit and the firing control circuit respectively, rendering the safe discharging circuit in the non-discharging state and the firing control circuit in the fire-forbidden state; Step B, the logic control circuit reading the detecting signal output by the detecting circuit: if the detecting signal does not change, continue to execute the Step B; if not, ending the charging process.

18. The detecting method according to any one of claims 11 to 17, characterized in that during the detecting processes, the voltage of the connecting end is always not higher than the safe voltage of the ignition unit.

19. The detecting method according to claim 18, characterized in that the safe voltage is the minimal voltage supplied by an ignition capacitor in the storage unit and needed by the ignition unit to ignite.

20. The detecting method according to any one of claims 11 to 17 or claim 19, characterized in that the maximal charging time is longer than the maximal discharging time in the safe discharging loop detecting process; the maximal discharging time in the safe discharging loop detecting process is longer than the maximal discharging time in the firing loop detecting process. 30 P39337