AU2003236154A1 - Circuit pattern dividing method, stencil mask manufacturing method, stencil mask, and exposure method - Google Patents

Circuit pattern dividing method, stencil mask manufacturing method, stencil mask, and exposure method

Info

Publication number
AU2003236154A1
AU2003236154A1 AU2003236154A AU2003236154A AU2003236154A1 AU 2003236154 A1 AU2003236154 A1 AU 2003236154A1 AU 2003236154 A AU2003236154 A AU 2003236154A AU 2003236154 A AU2003236154 A AU 2003236154A AU 2003236154 A1 AU2003236154 A1 AU 2003236154A1
Authority
AU
Australia
Prior art keywords
stencil mask
circuit pattern
pattern dividing
exposure
manufacturing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
AU2003236154A
Inventor
Hideyuki Eguchi
Hiroshi Sugimura
Akira Tamura
Takashi Yoshii
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toppan Inc
Original Assignee
Toppan Printing Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toppan Printing Co Ltd filed Critical Toppan Printing Co Ltd
Publication of AU2003236154A1 publication Critical patent/AU2003236154A1/en
Abandoned legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/16—Constructional details or arrangements
    • G06F1/20—Cooling means
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F1/00—Originals for photomechanical production of textured or patterned surfaces, e.g., masks, photo-masks, reticles; Mask blanks or pellicles therefor; Containers specially adapted therefor; Preparation thereof
    • G03F1/20—Masks or mask blanks for imaging by charged particle beam [CPB] radiation, e.g. by electron beam; Preparation thereof
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F1/00—Originals for photomechanical production of textured or patterned surfaces, e.g., masks, photo-masks, reticles; Mask blanks or pellicles therefor; Containers specially adapted therefor; Preparation thereof
    • G03F1/50—Mask blanks not covered by G03F1/20 - G03F1/34; Preparation thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
    • H01L21/0274—Photolithographic processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67011—Apparatus for manufacture or treatment

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Power Engineering (AREA)
  • Theoretical Computer Science (AREA)
  • Human Computer Interaction (AREA)
  • General Engineering & Computer Science (AREA)
  • Electron Beam Exposure (AREA)
  • Preparing Plates And Mask In Photomechanical Process (AREA)
AU2003236154A 2002-03-26 2003-03-26 Circuit pattern dividing method, stencil mask manufacturing method, stencil mask, and exposure method Abandoned AU2003236154A1 (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP2002-85748 2002-03-26
JP2002085748 2002-03-26
PCT/JP2003/003731 WO2003081649A1 (en) 2002-03-26 2003-03-26 Circuit pattern dividing method, stencil mask manufacturing method, stencil mask, and exposure method

Publications (1)

Publication Number Publication Date
AU2003236154A1 true AU2003236154A1 (en) 2003-10-08

Family

ID=28449269

Family Applications (1)

Application Number Title Priority Date Filing Date
AU2003236154A Abandoned AU2003236154A1 (en) 2002-03-26 2003-03-26 Circuit pattern dividing method, stencil mask manufacturing method, stencil mask, and exposure method

Country Status (8)

Country Link
US (1) US7181722B2 (en)
EP (1) EP1489644A1 (en)
JP (1) JP4314998B2 (en)
KR (1) KR100931552B1 (en)
CN (1) CN100380583C (en)
AU (1) AU2003236154A1 (en)
TW (1) TWI296823B (en)
WO (1) WO2003081649A1 (en)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8100847B2 (en) * 2007-10-25 2012-01-24 Fournet Ii Louis J Protective skin cover
US8369569B2 (en) * 2008-03-21 2013-02-05 Synopsys, Inc. Method and apparatus for detecting non-uniform fracturing of a photomask shape
CN102339329B (en) * 2010-07-19 2013-07-31 中国科学院微电子研究所 Method for dividing physical layout
US9854856B1 (en) 2012-04-13 2018-01-02 Jimmy R. Baldonado Safety vest
JP6988202B2 (en) * 2017-03-23 2022-01-05 大日本印刷株式会社 Mask for charged particle beam exposure and its manufacturing method

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3105580B2 (en) * 1991-07-29 2000-11-06 富士通株式会社 Method of making charged particle beam drawing mask and mask
JP3357927B2 (en) * 1993-07-09 2002-12-16 株式会社ニコン Charged particle beam exposure apparatus and charged particle beam exposure method
JP3491093B2 (en) * 1994-03-30 2004-01-26 株式会社ニコン Exposure data creation device for mask
JP3601630B2 (en) * 1995-11-01 2004-12-15 株式会社ニコン Charged particle beam transfer method
JP3360666B2 (en) * 1999-11-12 2002-12-24 日本電気株式会社 Drawing pattern verification method
JP3476410B2 (en) * 2000-03-01 2003-12-10 Ｎｅｃエレクトロニクス株式会社 Manufacturing method of exposure mask
JP3479024B2 (en) * 2000-03-28 2003-12-15 Ｎｅｃエレクトロニクス株式会社 Electron beam exposure mask and pattern design method thereof
US6855467B2 (en) * 2000-09-05 2005-02-15 Hoya Corporation Transfer mask, method of dividing pattern or transfer mask, and method of manufacturing transfer mask
JP2002260983A (en) * 2001-02-28 2002-09-13 Nec Corp Eb transfer mask and its manufacturing method
JP4746753B2 (en) * 2001-03-05 2011-08-10 ルネサスエレクトロニクス株式会社 Charged particle beam exposure mask forming method and pattern data processing program for forming charged particle beam mask
US6830852B2 (en) * 2001-07-19 2004-12-14 Nikon Corporation Stencil reticles for use in charged-particle-beam microlithography, and pattern-determination methods for such reticles
JP2003045786A (en) * 2001-08-01 2003-02-14 Seiko Instruments Inc Layout figure data division processing apparatus and method of stencil mask, and program for making computer perform layout figure data division processing of the stencil mask
JP2003092250A (en) * 2001-09-18 2003-03-28 Hitachi Ltd Semiconductor device and manufacturing method therefor
JP3686367B2 (en) * 2001-11-15 2005-08-24 株式会社ルネサステクノロジ Pattern forming method and semiconductor device manufacturing method

Also Published As

Publication number Publication date
TWI296823B (en) 2008-05-11
JP4314998B2 (en) 2009-08-19
US20050079426A1 (en) 2005-04-14
TW200305929A (en) 2003-11-01
US7181722B2 (en) 2007-02-20
KR20040111396A (en) 2004-12-31
EP1489644A1 (en) 2004-12-22
WO2003081649A1 (en) 2003-10-02
CN1643654A (en) 2005-07-20
KR100931552B1 (en) 2009-12-14
JPWO2003081649A1 (en) 2005-07-28
CN100380583C (en) 2008-04-09

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Legal Events

Date Code Title Description
MK6 Application lapsed section 142(2)(f)/reg. 8.3(3) - pct applic. not entering national phase