AU2002341703A1 - A system and method for shared decoding using a data replay scheme - Google Patents

A system and method for shared decoding using a data replay scheme

Info

Publication number
AU2002341703A1
AU2002341703A1 AU2002341703A AU2002341703A AU2002341703A1 AU 2002341703 A1 AU2002341703 A1 AU 2002341703A1 AU 2002341703 A AU2002341703 A AU 2002341703A AU 2002341703 A AU2002341703 A AU 2002341703A AU 2002341703 A1 AU2002341703 A1 AU 2002341703A1
Authority
AU
Australia
Prior art keywords
data replay
shared decoding
replay scheme
scheme
decoding
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
AU2002341703A
Inventor
Mark Greenberg
Manish Shah
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Digeo Inc
Original Assignee
Digeo Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US09/955,537 external-priority patent/US7161994B2/en
Priority claimed from US09/954,777 external-priority patent/US7167531B2/en
Application filed by Digeo Inc filed Critical Digeo Inc
Publication of AU2002341703A1 publication Critical patent/AU2002341703A1/en
Abandoned legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0056—Systems characterized by the type of code used
    • H04L1/0067—Rate matching
    • H04L1/0068—Rate matching by puncturing
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/37—Decoding methods or techniques, not specific to the particular type of coding provided for in groups H03M13/03 - H03M13/35
    • H03M13/39—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes
    • H03M13/41—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes using the Viterbi algorithm or Viterbi processors
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/37—Decoding methods or techniques, not specific to the particular type of coding provided for in groups H03M13/03 - H03M13/35
    • H03M13/39—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes
    • H03M13/41—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes using the Viterbi algorithm or Viterbi processors
    • H03M13/4107—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes using the Viterbi algorithm or Viterbi processors implementing add, compare, select [ACS] operations
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/65—Purpose and implementation aspects
    • H03M13/6561—Parallelized implementations
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0045—Arrangements at the receiver end
    • H04L1/0054—Maximum-likelihood or sequential decoding, e.g. Viterbi, Fano, ZJ algorithms
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N21/00—Selective content distribution, e.g. interactive television or video on demand [VOD]
    • H04N21/20—Servers specifically adapted for the distribution of content, e.g. VOD servers; Operations thereof
    • H04N21/23—Processing of content or additional data; Elementary server operations; Server middleware
    • H04N21/238—Interfacing the downstream path of the transmission network, e.g. adapting the transmission rate of a video stream to network bandwidth; Processing of multiplex streams
    • H04N21/2383—Channel coding or modulation of digital bit-stream, e.g. QPSK modulation
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N21/00—Selective content distribution, e.g. interactive television or video on demand [VOD]
    • H04N21/40—Client devices specifically adapted for the reception of or interaction with content, e.g. set-top-box [STB]; Operations thereof
    • H04N21/43—Processing of content or additional data, e.g. demultiplexing additional data from a digital video stream; Elementary client operations, e.g. monitoring of home network or synchronising decoder's clock; Client middleware
    • H04N21/438—Interfacing the downstream path of the transmission network originating from a server, e.g. retrieving MPEG packets from an IP network
    • H04N21/4382—Demodulation or channel decoding, e.g. QPSK demodulation
AU2002341703A 2001-09-17 2002-09-17 A system and method for shared decoding using a data replay scheme Abandoned AU2002341703A1 (en)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US09/955,537 US7161994B2 (en) 2001-09-17 2001-09-17 System and method for shared decoding
US09/954,777 US7167531B2 (en) 2001-09-17 2001-09-17 System and method for shared decoding using a data replay scheme
US09/955,537 2001-09-17
US09/954,777 2001-09-17
PCT/US2002/029592 WO2003026295A2 (en) 2001-09-17 2002-09-17 A system and method for shared decoding using a data replay scheme

Publications (1)

Publication Number Publication Date
AU2002341703A1 true AU2002341703A1 (en) 2003-04-01

Family

ID=27130355

Family Applications (1)

Application Number Title Priority Date Filing Date
AU2002341703A Abandoned AU2002341703A1 (en) 2001-09-17 2002-09-17 A system and method for shared decoding using a data replay scheme

Country Status (2)

Country Link
AU (1) AU2002341703A1 (en)
WO (1) WO2003026295A2 (en)

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2918088B2 (en) * 1994-02-10 1999-07-12 株式会社日立製作所 Hierarchical network management system and method for controlling network management information
US5802315A (en) * 1995-09-04 1998-09-01 Sharp Kabushiki Kaisha Picture reproducing apparatus
US5778192A (en) * 1995-10-26 1998-07-07 Motorola, Inc. Method and device for optimal bit allocation between different sources of information in digital video compression
JP3340343B2 (en) * 1997-03-13 2002-11-05 株式会社東芝 Processor and information processing device

Also Published As

Publication number Publication date
WO2003026295A2 (en) 2003-03-27
WO2003026295A3 (en) 2003-10-16

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Legal Events

Date Code Title Description
MK6 Application lapsed section 142(2)(f)/reg. 8.3(3) - pct applic. not entering national phase