AU2002310503A1 - Direct inner layer interconnect for a high speed printed circuit board - Google Patents

Direct inner layer interconnect for a high speed printed circuit board

Info

Publication number
AU2002310503A1
AU2002310503A1 AU2002310503A AU2002310503A AU2002310503A1 AU 2002310503 A1 AU2002310503 A1 AU 2002310503A1 AU 2002310503 A AU2002310503 A AU 2002310503A AU 2002310503 A AU2002310503 A AU 2002310503A AU 2002310503 A1 AU2002310503 A1 AU 2002310503A1
Authority
AU
Australia
Prior art keywords
circuit board
printed circuit
high speed
inner layer
layer interconnect
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
AU2002310503A
Inventor
Mark W. Gailus
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Teradyne Inc
Original Assignee
Teradyne Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Teradyne Inc filed Critical Teradyne Inc
Publication of AU2002310503A1 publication Critical patent/AU2002310503A1/en
Abandoned legal-status Critical Current

Links

AU2002310503A 2001-06-26 2002-06-24 Direct inner layer interconnect for a high speed printed circuit board Abandoned AU2002310503A1 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US09/892,045 2001-06-26

Publications (1)

Publication Number Publication Date
AU2002310503A1 true AU2002310503A1 (en) 2003-03-03

Family

ID=

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110581417A (en) * 2018-06-07 2019-12-17 奥特斯奥地利科技与系统技术有限公司 Deformation layer for short electrical connections between electrical device structures

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110581417A (en) * 2018-06-07 2019-12-17 奥特斯奥地利科技与系统技术有限公司 Deformation layer for short electrical connections between electrical device structures
CN110581417B (en) * 2018-06-07 2022-09-30 奥特斯奥地利科技与系统技术有限公司 Deformation layer for short electrical connection between electrical device structures

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