AU2002230582A1 - Two mask via pattern to improve pattern definition - Google Patents
Two mask via pattern to improve pattern definitionInfo
- Publication number
- AU2002230582A1 AU2002230582A1 AU2002230582A AU3058202A AU2002230582A1 AU 2002230582 A1 AU2002230582 A1 AU 2002230582A1 AU 2002230582 A AU2002230582 A AU 2002230582A AU 3058202 A AU3058202 A AU 3058202A AU 2002230582 A1 AU2002230582 A1 AU 2002230582A1
- Authority
- AU
- Australia
- Prior art keywords
- pattern
- improve
- mask via
- definition
- via pattern
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
Links
Classifications
-
- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
- G03F7/70—Microphotolithographic exposure; Apparatus therefor
- G03F7/70425—Imaging strategies, e.g. for increasing throughput or resolution, printing product fields larger than the image field or compensating lithography- or non-lithography errors, e.g. proximity correction, mix-and-match, stitching or double patterning
- G03F7/70466—Multiple exposures, e.g. combination of fine and coarse exposures, double patterning or multiple exposures for printing a single feature
-
- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F1/00—Originals for photomechanical production of textured or patterned surfaces, e.g., masks, photo-masks, reticles; Mask blanks or pellicles therefor; Containers specially adapted therefor; Preparation thereof
- G03F1/68—Preparation processes not covered by groups G03F1/20 - G03F1/50
- G03F1/70—Adapting basic layout or design of masks to lithographic process requirements, e.g., second iteration correction of mask patterns for imaging
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
Landscapes
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
- Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US71621800A | 2000-11-21 | 2000-11-21 | |
US09/716,218 | 2000-11-21 | ||
PCT/US2001/046242 WO2002043139A2 (en) | 2000-11-21 | 2001-10-30 | Two mask via pattern to improve pattern definition |
Publications (1)
Publication Number | Publication Date |
---|---|
AU2002230582A1 true AU2002230582A1 (en) | 2002-06-03 |
Family
ID=24877206
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
AU2002230582A Abandoned AU2002230582A1 (en) | 2000-11-21 | 2001-10-30 | Two mask via pattern to improve pattern definition |
Country Status (3)
Country | Link |
---|---|
US (1) | US20020106587A1 (en) |
AU (1) | AU2002230582A1 (en) |
WO (1) | WO2002043139A2 (en) |
Families Citing this family (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6803178B1 (en) | 2001-06-25 | 2004-10-12 | Advanced Micro Devices, Inc. | Two mask photoresist exposure pattern for dense and isolated regions |
SE522910C2 (en) * | 2002-06-03 | 2004-03-16 | Ericsson Telefon Ab L M | Integrated circuit for reducing current density in a transistor including intertwined collector, emitter and control fingers |
DE10229463B4 (en) * | 2002-07-01 | 2008-12-11 | Qimonda Ag | Semiconductor device and method for its production |
US7235489B2 (en) * | 2004-05-21 | 2007-06-26 | Agere Systems Inc. | Device and method to eliminate shorting induced by via to metal misalignment |
US20080038910A1 (en) * | 2006-08-10 | 2008-02-14 | Advanced Micro Devices, Inc. | Multiple lithography for reduced negative feature corner rounding |
TWI336904B (en) * | 2007-02-26 | 2011-02-01 | Nanya Technology Corp | Method for forming ring pattern |
US8872235B2 (en) | 2012-02-23 | 2014-10-28 | Infineon Technologies Austria Ag | Integrated Schottky diode for HEMTs |
US8716139B2 (en) * | 2012-03-01 | 2014-05-06 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of patterning a semiconductor device |
US9761436B2 (en) | 2014-06-30 | 2017-09-12 | Taiwan Semiconductor Manufacturing Company, Ltd. | Mechanisms for forming patterns using multiple lithography processes |
US9245763B2 (en) * | 2014-03-13 | 2016-01-26 | Taiwan Semiconductor Manufacturing Company, Ltd. | Mechanisms for forming patterns using multiple lithography processes |
US20190172770A1 (en) * | 2017-12-05 | 2019-06-06 | Infineon Technologies Austria Ag | Semiconductor Device with Integrated pn Diode Temperature Sensor |
Family Cites Families (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS58209124A (en) * | 1982-05-31 | 1983-12-06 | Toshiba Corp | Forming method for resist pattern |
-
2001
- 2001-02-23 US US09/790,537 patent/US20020106587A1/en not_active Abandoned
- 2001-10-30 AU AU2002230582A patent/AU2002230582A1/en not_active Abandoned
- 2001-10-30 WO PCT/US2001/046242 patent/WO2002043139A2/en active Application Filing
Also Published As
Publication number | Publication date |
---|---|
WO2002043139A2 (en) | 2002-05-30 |
US20020106587A1 (en) | 2002-08-08 |
WO2002043139A3 (en) | 2002-12-19 |
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