AU2002219840A1 - Copper alloys for interconnections having improved electromigration characteristics and methods of making same - Google Patents
Copper alloys for interconnections having improved electromigration characteristics and methods of making sameInfo
- Publication number
- AU2002219840A1 AU2002219840A1 AU2002219840A AU1984002A AU2002219840A1 AU 2002219840 A1 AU2002219840 A1 AU 2002219840A1 AU 2002219840 A AU2002219840 A AU 2002219840A AU 1984002 A AU1984002 A AU 1984002A AU 2002219840 A1 AU2002219840 A1 AU 2002219840A1
- Authority
- AU
- Australia
- Prior art keywords
- interconnections
- methods
- making same
- copper alloys
- improved electromigration
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
- H01L21/76849—Barrier, adhesion or liner layers formed in openings in a dielectric the layer being positioned on top of the main fill metal
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76853—Barrier, adhesion or liner layers characterized by particular after-treatment steps
- H01L21/76861—Post-treatment or after-treatment not introducing additional chemical elements into the layer
- H01L21/76864—Thermal treatment
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76867—Barrier, adhesion or liner layers characterized by methods of formation other than PVD, CVD or deposition from a liquids
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/53204—Conductive materials
- H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
- H01L23/53228—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
- H01L23/53238—Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Electrodes Of Semiconductors (AREA)
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US09/739,929 | 2000-12-18 | ||
US09/739,929 US6800554B2 (en) | 2000-12-18 | 2000-12-18 | Copper alloys for interconnections having improved electromigration characteristics and methods of making same |
PCT/US2001/043915 WO2002050882A2 (en) | 2000-12-18 | 2001-11-13 | Copper alloys for interconnections having improved electromigration characteristics and methods of making same |
Publications (1)
Publication Number | Publication Date |
---|---|
AU2002219840A1 true AU2002219840A1 (en) | 2002-07-01 |
Family
ID=24974359
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
AU2002219840A Abandoned AU2002219840A1 (en) | 2000-12-18 | 2001-11-13 | Copper alloys for interconnections having improved electromigration characteristics and methods of making same |
Country Status (4)
Country | Link |
---|---|
US (3) | US6800554B2 (en) |
AU (1) | AU2002219840A1 (en) |
TW (1) | TWI283455B (en) |
WO (1) | WO2002050882A2 (en) |
Families Citing this family (71)
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US6541858B1 (en) * | 1998-12-17 | 2003-04-01 | Micron Technology, Inc. | Interconnect alloys and methods and apparatus using same |
US6800554B2 (en) * | 2000-12-18 | 2004-10-05 | Intel Corporation | Copper alloys for interconnections having improved electromigration characteristics and methods of making same |
US7781327B1 (en) | 2001-03-13 | 2010-08-24 | Novellus Systems, Inc. | Resputtering process for eliminating dielectric damage |
US8043484B1 (en) | 2001-03-13 | 2011-10-25 | Novellus Systems, Inc. | Methods and apparatus for resputtering process that improves barrier coverage |
US6764940B1 (en) | 2001-03-13 | 2004-07-20 | Novellus Systems, Inc. | Method for depositing a diffusion barrier for copper interconnect applications |
KR100499557B1 (en) * | 2001-06-11 | 2005-07-07 | 주식회사 하이닉스반도체 | method for fabricating the wire of semiconductor device |
KR100418581B1 (en) * | 2001-06-12 | 2004-02-11 | 주식회사 하이닉스반도체 | Method of forming memory device |
US6727177B1 (en) | 2001-10-18 | 2004-04-27 | Lsi Logic Corporation | Multi-step process for forming a barrier film for use in copper layer formation |
US7115991B1 (en) * | 2001-10-22 | 2006-10-03 | Lsi Logic Corporation | Method for creating barriers for copper diffusion |
US6734101B1 (en) * | 2001-10-31 | 2004-05-11 | Taiwan Semiconductor Manufacturing Company | Solution to the problem of copper hillocks |
US6605874B2 (en) * | 2001-12-19 | 2003-08-12 | Intel Corporation | Method of making semiconductor device using an interconnect |
US6780772B2 (en) * | 2001-12-21 | 2004-08-24 | Nutool, Inc. | Method and system to provide electroplanarization of a workpiece with a conducting material layer |
US6911394B2 (en) * | 2002-02-25 | 2005-06-28 | Texas Instruments Incorporated | Semiconductor devices and methods of manufacturing such semiconductor devices |
US6656836B1 (en) * | 2002-03-18 | 2003-12-02 | Advanced Micro Devices, Inc. | Method of performing a two stage anneal in the formation of an alloy interconnect |
US7115498B1 (en) * | 2002-04-16 | 2006-10-03 | Advanced Micro Devices, Inc. | Method of ultra-low energy ion implantation to form alloy layers in copper |
US6861349B1 (en) * | 2002-05-15 | 2005-03-01 | Advanced Micro Devices, Inc. | Method of forming an adhesion layer with an element reactive with a barrier layer |
US7074709B2 (en) * | 2002-06-28 | 2006-07-11 | Texas Instruments Incorporated | Localized doping and/or alloying of metallization for increased interconnect performance |
US6992004B1 (en) * | 2002-07-31 | 2006-01-31 | Advanced Micro Devices, Inc. | Implanted barrier layer to improve line reliability and method of forming same |
US6727175B2 (en) * | 2002-08-02 | 2004-04-27 | Micron Technology, Inc. | Method of controlling metal formation processes using ion implantation, and system for performing same |
US20040056366A1 (en) * | 2002-09-25 | 2004-03-25 | Maiz Jose A. | A method of forming surface alteration of metal interconnect in integrated circuits for electromigration and adhesion improvement |
US7727892B2 (en) * | 2002-09-25 | 2010-06-01 | Intel Corporation | Method and apparatus for forming metal-metal oxide etch stop/barrier for integrated circuit interconnects |
US20040061237A1 (en) * | 2002-09-26 | 2004-04-01 | Advanced Micro Devices, Inc. | Method of reducing voiding in copper interconnects with copper alloys in the seed layer |
US6706629B1 (en) * | 2003-01-07 | 2004-03-16 | Taiwan Semiconductor Manufacturing Company | Barrier-free copper interconnect |
US20040175926A1 (en) * | 2003-03-07 | 2004-09-09 | Advanced Micro Devices, Inc. | Method for manufacturing a semiconductor component having a barrier-lined opening |
US8298933B2 (en) | 2003-04-11 | 2012-10-30 | Novellus Systems, Inc. | Conformal films on semiconductor substrates |
US7842605B1 (en) | 2003-04-11 | 2010-11-30 | Novellus Systems, Inc. | Atomic layer profiling of diffusion barrier and metal seed layers |
JP2004349609A (en) * | 2003-05-26 | 2004-12-09 | Renesas Technology Corp | Semiconductor device and its manufacturing method |
JP3722813B2 (en) * | 2003-07-08 | 2005-11-30 | 沖電気工業株式会社 | Method for forming buried wiring structure |
KR100546209B1 (en) * | 2003-07-09 | 2006-01-24 | 매그나칩 반도체 유한회사 | Copper wiring formation method of semiconductor device |
US7026244B2 (en) * | 2003-08-08 | 2006-04-11 | Taiwan Semiconductor Manufacturing Co., Ltd. | Low resistance and reliable copper interconnects by variable doping |
DE10339990B8 (en) * | 2003-08-29 | 2013-01-31 | Advanced Micro Devices, Inc. | A method of fabricating a metal line having increased resistance to electromigration along an interface of a dielectric barrier layer by implanting material into the metal line |
US7169706B2 (en) * | 2003-10-16 | 2007-01-30 | Advanced Micro Devices, Inc. | Method of using an adhesion precursor layer for chemical vapor deposition (CVD) copper deposition |
US7229922B2 (en) * | 2003-10-27 | 2007-06-12 | Intel Corporation | Method for making a semiconductor device having increased conductive material reliability |
US6998343B1 (en) | 2003-11-24 | 2006-02-14 | Lsi Logic Corporation | Method for creating barrier layers for copper diffusion |
KR100552812B1 (en) * | 2003-12-31 | 2006-02-22 | 동부아남반도체 주식회사 | Cu LINE FORMATION METHOD OF SEMICONDUCTOR DEVICE |
WO2006001356A1 (en) * | 2004-06-24 | 2006-01-05 | Nec Corporation | Semiconductor device and method for manufacturing same |
US20060001170A1 (en) * | 2004-07-01 | 2006-01-05 | Fan Zhang | Conductive compound cap layer |
US7169700B2 (en) * | 2004-08-06 | 2007-01-30 | Taiwan Semiconductor Manufacturing Co., Ltd. | Metal interconnect features with a doping gradient |
JP2006165115A (en) * | 2004-12-03 | 2006-06-22 | Toshiba Corp | Semiconductor device |
US7855147B1 (en) | 2006-06-22 | 2010-12-21 | Novellus Systems, Inc. | Methods and apparatus for engineering an interface between a diffusion barrier layer and a seed layer |
US7352229B1 (en) * | 2006-07-10 | 2008-04-01 | Altera Corporation | Reference clock receiver compliant with LVPECL, LVDS and PCI-Express supporting both AC coupling and DC coupling |
US20080073795A1 (en) * | 2006-09-24 | 2008-03-27 | Georgia Tech Research Corporation | Integrated circuit interconnection devices and methods |
US7510634B1 (en) | 2006-11-10 | 2009-03-31 | Novellus Systems, Inc. | Apparatus and methods for deposition and/or etch selectivity |
US7682966B1 (en) | 2007-02-01 | 2010-03-23 | Novellus Systems, Inc. | Multistep method of depositing metal seed layers |
US20100200991A1 (en) * | 2007-03-15 | 2010-08-12 | Rohan Akolkar | Dopant Enhanced Interconnect |
DE102007020252A1 (en) * | 2007-04-30 | 2008-11-06 | Advanced Micro Devices, Inc., Sunnyvale | Technique for making metal lines in a semiconductor by adjusting the temperature dependence of the line resistance |
US7922880B1 (en) | 2007-05-24 | 2011-04-12 | Novellus Systems, Inc. | Method and apparatus for increasing local plasma density in magnetically confined plasma |
US7897516B1 (en) | 2007-05-24 | 2011-03-01 | Novellus Systems, Inc. | Use of ultra-high magnetic fields in resputter and plasma etching |
DE102008007001B4 (en) * | 2008-01-31 | 2016-09-22 | Globalfoundries Dresden Module One Limited Liability Company & Co. Kg | Increasing the resistance to electromigration in a connection structure of a semiconductor device by forming an alloy |
US7843063B2 (en) * | 2008-02-14 | 2010-11-30 | International Business Machines Corporation | Microstructure modification in copper interconnect structure |
JP4836092B2 (en) | 2008-03-19 | 2011-12-14 | 国立大学法人東北大学 | Method for forming semiconductor device |
US8017523B1 (en) * | 2008-05-16 | 2011-09-13 | Novellus Systems, Inc. | Deposition of doped copper seed layers having improved reliability |
US8358007B2 (en) * | 2009-06-11 | 2013-01-22 | Globalfoundries Singapore Pte. Ltd. | Integrated circuit system employing low-k dielectrics and method of manufacture thereof |
FR2963160A1 (en) * | 2010-07-22 | 2012-01-27 | St Microelectronics Crolles 2 | METHOD FOR PRODUCING A METALLIZATION LEVEL AND A VIA LEVEL AND CORRESPONDING INTEGRATED CIRCUIT |
KR101755635B1 (en) * | 2010-10-14 | 2017-07-10 | 삼성전자주식회사 | Semiconductor device and method of fabricating the same |
US8736055B2 (en) * | 2012-03-01 | 2014-05-27 | Lam Research Corporation | Methods and layers for metallization |
US9059176B2 (en) | 2012-04-20 | 2015-06-16 | International Business Machines Corporation | Copper interconnect with CVD liner and metallic cap |
US8791005B2 (en) | 2012-06-18 | 2014-07-29 | International Business Machines Corporation | Sidewalls of electroplated copper interconnects |
US8765602B2 (en) | 2012-08-30 | 2014-07-01 | International Business Machines Corporation | Doping of copper wiring structures in back end of line processing |
US20140138837A1 (en) * | 2012-11-20 | 2014-05-22 | Stmicroelectronics, Inc. | Sandwiched diffusion barrier and metal liner for an interconnect structure |
US8729702B1 (en) * | 2012-11-20 | 2014-05-20 | Stmicroelectronics, Inc. | Copper seed layer for an interconnect structure having a doping concentration level gradient |
US10170425B2 (en) * | 2014-11-12 | 2019-01-01 | International Business Machines Corporation | Microstructure of metal interconnect layer |
TWI583620B (en) * | 2015-06-09 | 2017-05-21 | A Method for Making Micron Welded Copper Wire with Oxidation and Etching of Copper | |
US9754891B2 (en) | 2015-09-23 | 2017-09-05 | International Business Machines Corporation | Low-temperature diffusion doping of copper interconnects independent of seed layer composition |
US9780035B1 (en) | 2016-06-30 | 2017-10-03 | International Business Machines Corporation | Structure and method for improved stabilization of cobalt cap and/or cobalt liner in interconnects |
US10304729B2 (en) | 2016-11-29 | 2019-05-28 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of forming interconnect structures |
DE102017104742A1 (en) * | 2017-03-07 | 2018-09-13 | Osram Opto Semiconductors Gmbh | Optoelectronic component and method for producing an optoelectronic component |
DE102017106410A1 (en) | 2017-03-24 | 2018-09-27 | Osram Opto Semiconductors Gmbh | Method for producing an optoelectronic component and optoelectronic component |
US11508617B2 (en) | 2019-10-24 | 2022-11-22 | Applied Materials, Inc. | Method of forming interconnect for semiconductor device |
US11257677B2 (en) * | 2020-01-24 | 2022-02-22 | Applied Materials, Inc. | Methods and devices for subtractive self-alignment |
CN118186248A (en) * | 2022-12-12 | 2024-06-14 | 华为技术有限公司 | Copper-based composite material, preparation method thereof, PCB, integrated circuit and electronic equipment |
Family Cites Families (18)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6268291B1 (en) * | 1995-12-29 | 2001-07-31 | International Business Machines Corporation | Method for forming electromigration-resistant structures by doping |
US6037257A (en) * | 1997-05-08 | 2000-03-14 | Applied Materials, Inc. | Sputter deposition and annealing of copper alloy metallization |
US5933758A (en) | 1997-05-12 | 1999-08-03 | Motorola, Inc. | Method for preventing electroplating of copper on an exposed surface at the edge exclusion of a semiconductor wafer |
JP3540699B2 (en) | 1998-01-12 | 2004-07-07 | 松下電器産業株式会社 | Method for manufacturing semiconductor device |
US6022808A (en) * | 1998-03-16 | 2000-02-08 | Advanced Micro Devices, Inc. | Copper interconnect methodology for enhanced electromigration resistance |
US6130156A (en) * | 1998-04-01 | 2000-10-10 | Texas Instruments Incorporated | Variable doping of metal plugs for enhanced reliability |
US6117770A (en) * | 1998-10-08 | 2000-09-12 | Advanced Micro Devices, Inc. | Method for implanting semiconductor conductive layers |
US6303498B1 (en) * | 1999-08-20 | 2001-10-16 | Taiwan Semiconductor Manufacturing Company | Method for preventing seed layer oxidation for high aspect gap fill |
US6136707A (en) * | 1999-10-02 | 2000-10-24 | Cohen; Uri | Seed layers for interconnects and methods for fabricating such seed layers |
US6924226B2 (en) * | 1999-10-02 | 2005-08-02 | Uri Cohen | Methods for making multiple seed layers for metallic interconnects |
US6610151B1 (en) * | 1999-10-02 | 2003-08-26 | Uri Cohen | Seed layers for interconnects and methods and apparatus for their fabrication |
US6479389B1 (en) * | 1999-10-04 | 2002-11-12 | Taiwan Semiconductor Manufacturing Company | Method of doping copper metallization |
US6440849B1 (en) * | 1999-10-18 | 2002-08-27 | Agere Systems Guardian Corp. | Microstructure control of copper interconnects |
US6689689B1 (en) * | 2000-01-05 | 2004-02-10 | Advanced Micro Devices, Inc. | Selective deposition process for allowing damascene-type Cu interconnect lines |
US6426289B1 (en) * | 2000-03-24 | 2002-07-30 | Micron Technology, Inc. | Method of fabricating a barrier layer associated with a conductor layer in damascene structures |
US6607640B2 (en) * | 2000-03-29 | 2003-08-19 | Applied Materials, Inc. | Temperature control of a substrate |
US6228759B1 (en) * | 2000-05-02 | 2001-05-08 | Advanced Micro Devices, Inc. | Method of forming an alloy precipitate to surround interconnect to minimize electromigration |
US6800554B2 (en) * | 2000-12-18 | 2004-10-05 | Intel Corporation | Copper alloys for interconnections having improved electromigration characteristics and methods of making same |
-
2000
- 2000-12-18 US US09/739,929 patent/US6800554B2/en not_active Expired - Fee Related
-
2001
- 2001-11-13 AU AU2002219840A patent/AU2002219840A1/en not_active Abandoned
- 2001-11-13 WO PCT/US2001/043915 patent/WO2002050882A2/en not_active Application Discontinuation
- 2001-11-16 TW TW090128504A patent/TWI283455B/en not_active IP Right Cessation
-
2004
- 2004-06-01 US US10/859,327 patent/US7220674B2/en not_active Expired - Fee Related
- 2004-06-02 US US10/860,428 patent/US6977220B2/en not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
US20040224507A1 (en) | 2004-11-11 |
US6977220B2 (en) | 2005-12-20 |
TWI283455B (en) | 2007-07-01 |
US7220674B2 (en) | 2007-05-22 |
WO2002050882A3 (en) | 2003-02-13 |
WO2002050882A2 (en) | 2002-06-27 |
US20040219788A1 (en) | 2004-11-04 |
US6800554B2 (en) | 2004-10-05 |
US20020076925A1 (en) | 2002-06-20 |
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