AU2001291138A1 - Apparatus for implementing a buffered daisy-chain connection between a memory controller and memory modules - Google Patents

Apparatus for implementing a buffered daisy-chain connection between a memory controller and memory modules

Info

Publication number
AU2001291138A1
AU2001291138A1 AU2001291138A AU9113801A AU2001291138A1 AU 2001291138 A1 AU2001291138 A1 AU 2001291138A1 AU 2001291138 A AU2001291138 A AU 2001291138A AU 9113801 A AU9113801 A AU 9113801A AU 2001291138 A1 AU2001291138 A1 AU 2001291138A1
Authority
AU
Australia
Prior art keywords
daisy
buffered
implementing
chain connection
memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
AU2001291138A
Inventor
Randy Bonella
James Dodd
John Halbert
Chung Lam
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Intel Corp
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Publication of AU2001291138A1 publication Critical patent/AU2001291138A1/en
Abandoned legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/12—Group selection circuits, e.g. for memory block selection, chip selection, array selection
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4063—Device-to-bus coupling
    • G06F13/409—Mechanical coupling
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4247—Bus transfer protocol, e.g. handshake; Synchronisation on a daisy chain bus
    • G06F13/4256—Bus transfer protocol, e.g. handshake; Synchronisation on a daisy chain bus using a clocked protocol
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/02—Disposition of storage elements, e.g. in the form of a matrix array
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Dram (AREA)
  • Memory System (AREA)
  • Bus Control (AREA)
  • Static Random-Access Memory (AREA)
AU2001291138A 2000-09-18 2001-09-18 Apparatus for implementing a buffered daisy-chain connection between a memory controller and memory modules Abandoned AU2001291138A1 (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US09/665,196 US6317352B1 (en) 2000-09-18 2000-09-18 Apparatus for implementing a buffered daisy chain connection between a memory controller and memory modules
US09/665,196 2000-09-18
PCT/US2001/029383 WO2002023550A2 (en) 2000-09-18 2001-09-18 Apparatus for implementing a buffered daisy-chain connection between a memory controller and memory modules

Publications (1)

Publication Number Publication Date
AU2001291138A1 true AU2001291138A1 (en) 2002-03-26

Family

ID=24669114

Family Applications (1)

Application Number Title Priority Date Filing Date
AU2001291138A Abandoned AU2001291138A1 (en) 2000-09-18 2001-09-18 Apparatus for implementing a buffered daisy-chain connection between a memory controller and memory modules

Country Status (7)

Country Link
US (1) US6317352B1 (en)
JP (1) JP4142950B2 (en)
KR (1) KR100531426B1 (en)
CN (1) CN1271533C (en)
AU (1) AU2001291138A1 (en)
TW (1) TWI231508B (en)
WO (1) WO2002023550A2 (en)

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