AU2001283568A1 - Method and system for hiding refreshes in a dynamic random access memory - Google Patents

Method and system for hiding refreshes in a dynamic random access memory

Info

Publication number
AU2001283568A1
AU2001283568A1 AU2001283568A AU8356801A AU2001283568A1 AU 2001283568 A1 AU2001283568 A1 AU 2001283568A1 AU 2001283568 A AU2001283568 A AU 2001283568A AU 8356801 A AU8356801 A AU 8356801A AU 2001283568 A1 AU2001283568 A1 AU 2001283568A1
Authority
AU
Australia
Prior art keywords
arrays
refreshed
array
data
random access
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
AU2001283568A
Inventor
Charles H Dennison
Brent Keeth
Kevin J. Ryan
Brian M. Shirley
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Micron Technology Inc
Original Assignee
Micron Technology Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Micron Technology Inc filed Critical Micron Technology Inc
Publication of AU2001283568A1 publication Critical patent/AU2001283568A1/en
Abandoned legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/406—Management or control of the refreshing or charge-regeneration cycles
    • G11C11/40618—Refresh operations over multiple banks or interleaving
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/406—Management or control of the refreshing or charge-regeneration cycles
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
    • G11C7/1042—Read-write modes for single port memories, i.e. having either a random port or a serial port using interleaving techniques, i.e. read-write of one part of the memory while preparing another part

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Dram (AREA)
  • Closed-Circuit Television Systems (AREA)

Abstract

A method and system for refreshing a dynamic random access memory ("DRAM") (40) includes a pair of memory arrays for each of a plurality of banks. The DRAM (40) includes the usual addressing and data path circuitry, as well as a refresh controller (70) that refreshes the arrays in a manner that hides refreshes sufficiently that the DRAM (40) can be used in place of an SRAM as a cache memory (236). Since only one of the arrays in each bank is refreshed at a time, the refresh controller (70) is able to allow data to be written to the array that is not being refreshed. The refresh controller (70) then causes the write data to be temporarily stored so that it can be written to the array of the refresh of the array has been completed. If neither array is being refreshed, the data are written to both arrays. Data are read from the arrays by first checking to determine if any of the arrays is being refreshed. If so, data are read from the array that is not being refreshed.
AU2001283568A 2000-08-17 2001-08-14 Method and system for hiding refreshes in a dynamic random access memory Abandoned AU2001283568A1 (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US09/641,881 US6445636B1 (en) 2000-08-17 2000-08-17 Method and system for hiding refreshes in a dynamic random access memory
US09641881 2000-08-17
PCT/US2001/041725 WO2002015194A1 (en) 2000-08-17 2001-08-14 Method and system for hiding refreshes in a dynamic random access memory

Publications (1)

Publication Number Publication Date
AU2001283568A1 true AU2001283568A1 (en) 2002-02-25

Family

ID=24574243

Family Applications (1)

Application Number Title Priority Date Filing Date
AU2001283568A Abandoned AU2001283568A1 (en) 2000-08-17 2001-08-14 Method and system for hiding refreshes in a dynamic random access memory

Country Status (9)

Country Link
US (1) US6445636B1 (en)
EP (2) EP1328942B1 (en)
JP (1) JP2004507856A (en)
KR (1) KR100796179B1 (en)
CN (1) CN100570739C (en)
AT (1) ATE484831T1 (en)
AU (1) AU2001283568A1 (en)
DE (1) DE60143268D1 (en)
WO (1) WO2002015194A1 (en)

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US6697909B1 (en) * 2000-09-12 2004-02-24 International Business Machines Corporation Method and apparatus for performing data access and refresh operations in different sub-arrays of a DRAM cache memory
US6779076B1 (en) 2000-10-05 2004-08-17 Micron Technology, Inc. Method and system for using dynamic random access memory as cache memory
TW523759B (en) * 2001-08-03 2003-03-11 Umax Data Systems Inc Circuit architecture with extended general purpose input/output pin
US7149824B2 (en) * 2002-07-10 2006-12-12 Micron Technology, Inc. Dynamically setting burst length of memory device by applying signal to at least one external pin during a read or write transaction
US7224631B2 (en) * 2004-08-31 2007-05-29 Micron Technology, Inc. Non-skipping auto-refresh in a DRAM
US20060190678A1 (en) * 2005-02-22 2006-08-24 Butler Douglas B Static random access memory (SRAM) compatible, high availability memory array and method employing synchronous dynamic random access memory (DRAM) in conjunction with a single DRAM cache and tag
US7506100B2 (en) * 2005-02-23 2009-03-17 United Memories, Inc. Static random access memory (SRAM) compatible, high availability memory array and method employing synchronous dynamic random access memory (DRAM) in conjunction with a data cache and separate read and write registers and tag blocks
US7123521B1 (en) 2005-04-27 2006-10-17 Micron Technology, Inc. Random cache read
US7313047B2 (en) * 2006-02-23 2007-12-25 Hynix Semiconductor Inc. Dynamic semiconductor memory with improved refresh mechanism
WO2009073512A1 (en) * 2007-11-29 2009-06-11 Dow Global Technologies Inc. Compounds and methods of forming compounds useful as a toner
US7408813B2 (en) * 2006-08-03 2008-08-05 Micron Technology, Inc. Block erase for volatile memory
JP4781229B2 (en) * 2006-11-01 2011-09-28 キヤノン株式会社 Distortion correction apparatus, imaging apparatus, and control method for distortion correction apparatus
KR100940868B1 (en) 2009-05-25 2010-02-09 이성재 Device realizing read characteristic of sram from dram and method of the same
CN102081964B (en) * 2009-11-30 2014-12-10 国际商业机器公司 Method and system for refreshing dynamic random access memory
TWI670711B (en) 2010-09-14 2019-09-01 日商半導體能源研究所股份有限公司 Memory device and semiconductor device
KR20130042236A (en) * 2011-10-18 2013-04-26 에스케이하이닉스 주식회사 Memory system
KR101970712B1 (en) * 2012-08-23 2019-04-22 삼성전자주식회사 Device and method for moving data in terminal
CN103700393B (en) 2012-09-28 2016-08-03 国际商业机器公司 Intermediate circuit and method for DRAM
CA3146951A1 (en) 2014-03-27 2015-10-01 Techtronic Power Tools Technology Limited Powered fastener driver and operating method thereof
US9824737B2 (en) * 2015-12-22 2017-11-21 Intel Corporation Memory circuit and method for operating a first and a second set of memory cells in direct memory access mode with refresh
US10346093B1 (en) * 2018-03-16 2019-07-09 Xilinx, Inc. Memory arrangement for tensor data

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US5442588A (en) * 1994-08-16 1995-08-15 Cirrus Logic, Inc. Circuits and methods for refreshing a dual bank memory
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US5687132A (en) * 1995-10-26 1997-11-11 Cirrus Logic, Inc. Multiple-bank memory architecture and systems and methods using the same
JPH1011348A (en) * 1996-06-24 1998-01-16 Ricoh Co Ltd Controller for dram, and the dram
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Also Published As

Publication number Publication date
CN100570739C (en) 2009-12-16
WO2002015194A1 (en) 2002-02-21
EP1328942A1 (en) 2003-07-23
ATE484831T1 (en) 2010-10-15
KR100796179B1 (en) 2008-01-21
DE60143268D1 (en) 2010-11-25
EP2267722A1 (en) 2010-12-29
CN1471710A (en) 2004-01-28
US6445636B1 (en) 2002-09-03
KR20030088020A (en) 2003-11-15
JP2004507856A (en) 2004-03-11
EP1328942B1 (en) 2010-10-13
EP1328942A4 (en) 2008-01-02
EP2267722A8 (en) 2011-05-18

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