AU2001275512A1 - Method and system for automated processor register instantiation - Google Patents

Method and system for automated processor register instantiation

Info

Publication number
AU2001275512A1
AU2001275512A1 AU2001275512A AU7551201A AU2001275512A1 AU 2001275512 A1 AU2001275512 A1 AU 2001275512A1 AU 2001275512 A AU2001275512 A AU 2001275512A AU 7551201 A AU7551201 A AU 7551201A AU 2001275512 A1 AU2001275512 A1 AU 2001275512A1
Authority
AU
Australia
Prior art keywords
instantiation
processor register
automated processor
automated
register
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
AU2001275512A
Inventor
Gary Chard
T-Pinn Koh
Christopher Opoczynski
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Network Communications Inc
Original Assignee
Fujitsu Network Communications Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Network Communications Inc filed Critical Fujitsu Network Communications Inc
Publication of AU2001275512A1 publication Critical patent/AU2001275512A1/en
Abandoned legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Evolutionary Computation (AREA)
  • Geometry (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Executing Machine-Instructions (AREA)
  • Stored Programmes (AREA)
AU2001275512A 2000-06-06 2001-06-06 Method and system for automated processor register instantiation Abandoned AU2001275512A1 (en)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US21017100P 2000-06-06 2000-06-06
US60/210,171 2000-06-06
US09/875,575 US6721937B2 (en) 2000-06-06 2001-06-05 Method and system for automated processor register instantiation
US09/875,575 2001-06-05
PCT/US2001/040854 WO2001095165A2 (en) 2000-06-06 2001-06-06 Method and system for automated processor register instantiation

Publications (1)

Publication Number Publication Date
AU2001275512A1 true AU2001275512A1 (en) 2001-12-17

Family

ID=26904894

Family Applications (1)

Application Number Title Priority Date Filing Date
AU2001275512A Abandoned AU2001275512A1 (en) 2000-06-06 2001-06-06 Method and system for automated processor register instantiation

Country Status (3)

Country Link
US (1) US6721937B2 (en)
AU (1) AU2001275512A1 (en)
WO (1) WO2001095165A2 (en)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6952810B2 (en) * 2002-05-01 2005-10-04 Sun Microsystems, Inc. Coding speed and correctness of hardware description language (HDL) descriptions of hardware
US7707351B2 (en) * 2002-10-31 2010-04-27 Ring Technology Enterprises Of Texas, Llc Methods and systems for an identifier-based memory section
JP5050985B2 (en) * 2008-04-30 2012-10-17 富士通株式会社 Verification support program, verification support apparatus, and verification support method
JP5163350B2 (en) * 2008-05-19 2013-03-13 富士通株式会社 Verification support program, verification support apparatus, and verification support method
CN105278938A (en) * 2014-06-30 2016-01-27 深圳市中兴微电子技术有限公司 Chip integration method and apparatus
CN112364581B (en) * 2020-11-13 2023-07-25 上海兆芯集成电路股份有限公司 Method and device for automatically inserting specific codes into register transmission level design file

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5598344A (en) * 1990-04-06 1997-01-28 Lsi Logic Corporation Method and system for creating, validating, and scaling structural description of electronic device
US5541849A (en) 1990-04-06 1996-07-30 Lsi Logic Corporation Method and system for creating and validating low level description of electronic design from higher level, behavior-oriented description, including estimation and comparison of timing parameters
CA2126265A1 (en) 1993-09-27 1995-03-28 Michael Robert Cantone System for synthesizing field programmable gate array implementations from high level circuit descriptions
US5752035A (en) * 1995-04-05 1998-05-12 Xilinx, Inc. Method for compiling and executing programs for reprogrammable instruction set accelerator
US5867400A (en) * 1995-05-17 1999-02-02 International Business Machines Corporation Application specific processor and design method for same
JP2869379B2 (en) 1996-03-15 1999-03-10 三菱電機株式会社 Processor synthesis system and processor synthesis method
US6298370B1 (en) * 1997-04-04 2001-10-02 Texas Instruments Incorporated Computer operating process allocating tasks between first and second processors at run time based upon current processor load
US6519756B1 (en) * 1999-10-05 2003-02-11 Sun Microsystems, Inc. Method and apparatus for building an integrated circuit

Also Published As

Publication number Publication date
US6721937B2 (en) 2004-04-13
US20020054536A1 (en) 2002-05-09
WO2001095165A3 (en) 2003-01-30
WO2001095165A2 (en) 2001-12-13

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