AU2001275454A1 - Method for identifying the cause of yield loss in integrated circuit manufacture - Google Patents
Method for identifying the cause of yield loss in integrated circuit manufactureInfo
- Publication number
- AU2001275454A1 AU2001275454A1 AU2001275454A AU7545401A AU2001275454A1 AU 2001275454 A1 AU2001275454 A1 AU 2001275454A1 AU 2001275454 A AU2001275454 A AU 2001275454A AU 7545401 A AU7545401 A AU 7545401A AU 2001275454 A1 AU2001275454 A1 AU 2001275454A1
- Authority
- AU
- Australia
- Prior art keywords
- identifying
- cause
- integrated circuit
- yield loss
- circuit manufacture
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
Links
Classifications
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01N—INVESTIGATING OR ANALYSING MATERIALS BY DETERMINING THEIR CHEMICAL OR PHYSICAL PROPERTIES
- G01N21/00—Investigating or analysing materials by the use of optical means, i.e. using sub-millimetre waves, infrared, visible or ultraviolet light
- G01N21/84—Systems specially adapted for particular applications
- G01N21/88—Investigating the presence of flaws or contamination
- G01N21/95—Investigating the presence of flaws or contamination characterised by the material or shape of the object to be examined
- G01N21/9501—Semiconductor wafers
Landscapes
- Physics & Mathematics (AREA)
- Health & Medical Sciences (AREA)
- Life Sciences & Earth Sciences (AREA)
- Chemical & Material Sciences (AREA)
- Analytical Chemistry (AREA)
- Biochemistry (AREA)
- General Health & Medical Sciences (AREA)
- General Physics & Mathematics (AREA)
- Immunology (AREA)
- Pathology (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US09/591,603 US6701477B1 (en) | 2000-06-09 | 2000-06-09 | Method for identifying the cause of yield loss in integrated circuit manufacture |
US09591603 | 2000-06-09 | ||
PCT/US2001/018732 WO2001096835A2 (en) | 2000-06-09 | 2001-06-08 | Method for identifying the cause of yield loss in integrated circuit manufacture |
Publications (1)
Publication Number | Publication Date |
---|---|
AU2001275454A1 true AU2001275454A1 (en) | 2001-12-24 |
Family
ID=24367119
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
AU2001275454A Abandoned AU2001275454A1 (en) | 2000-06-09 | 2001-06-08 | Method for identifying the cause of yield loss in integrated circuit manufacture |
Country Status (3)
Country | Link |
---|---|
US (1) | US6701477B1 (en) |
AU (1) | AU2001275454A1 (en) |
WO (1) | WO2001096835A2 (en) |
Families Citing this family (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3870052B2 (en) * | 2001-09-20 | 2007-01-17 | 株式会社日立製作所 | Semiconductor device manufacturing method and defect inspection data processing method |
US7114143B2 (en) * | 2003-10-29 | 2006-09-26 | Lsi Logic Corporation | Process yield learning |
TW200622275A (en) * | 2004-09-06 | 2006-07-01 | Mentor Graphics Corp | Integrated circuit yield and quality analysis methods and systems |
US7310788B2 (en) * | 2005-02-24 | 2007-12-18 | International Business Machines Corporation | Sample probability of fault function determination using critical defect size map |
US7218984B1 (en) | 2005-12-16 | 2007-05-15 | International Business Machines Corporation | Dynamically determining yield expectation |
US7596736B2 (en) * | 2006-03-24 | 2009-09-29 | International Business Machines Corporation | Iterative process for identifying systematics in data |
US7954018B2 (en) * | 2007-02-02 | 2011-05-31 | Rudolph Technologies, Inc | Analysis techniques for multi-level memory |
US7853848B2 (en) * | 2007-10-22 | 2010-12-14 | International Business Machines Corporation | System and method for signature-based systematic condition detection and analysis |
US7890900B2 (en) * | 2008-08-19 | 2011-02-15 | Synopsys, Inc. | Various methods and apparatuses for effective yield enhancement of good chip dies having memories per wafer |
JP5342199B2 (en) * | 2008-09-19 | 2013-11-13 | ルネサスエレクトロニクス株式会社 | Failure rate prediction method, failure rate prediction program, semiconductor manufacturing device management method, and semiconductor device manufacturing method |
JP2010192026A (en) * | 2009-02-17 | 2010-09-02 | Toshiba Corp | Failure analysis method, failure analysis system, and memory macro system |
US8799732B2 (en) * | 2012-02-09 | 2014-08-05 | International Business Machines Corporation | Methodology for correlated memory fail estimations |
US9411007B2 (en) * | 2012-10-29 | 2016-08-09 | The Regents Of The University Of Michigan | System and method for statistical post-silicon validation |
Family Cites Families (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5475695A (en) | 1993-03-19 | 1995-12-12 | Semiconductor Diagnosis & Test Corporation | Automatic failure analysis system |
US5497381A (en) * | 1993-10-15 | 1996-03-05 | Analog Devices, Inc. | Bitstream defect analysis method for integrated circuits |
US5515384A (en) * | 1994-03-01 | 1996-05-07 | International Business Machines Corporation | Method and system of fault diagnosis of application specific electronic circuits |
US5991699A (en) * | 1995-05-04 | 1999-11-23 | Kla Instruments Corporation | Detecting groups of defects in semiconductor feature space |
US5539752A (en) | 1995-06-30 | 1996-07-23 | Advanced Micro Devices, Inc. | Method and system for automated analysis of semiconductor defect data |
US5777901A (en) | 1995-09-29 | 1998-07-07 | Advanced Micro Devices, Inc. | Method and system for automated die yield prediction in semiconductor manufacturing |
US5822218A (en) | 1996-08-27 | 1998-10-13 | Clemson University | Systems, methods and computer program products for prediction of defect-related failures in integrated circuits |
US5982920A (en) * | 1997-01-08 | 1999-11-09 | Lockheed Martin Energy Research Corp. Oak Ridge National Laboratory | Automated defect spatial signature analysis for semiconductor manufacturing process |
US6408219B2 (en) * | 1998-05-11 | 2002-06-18 | Applied Materials, Inc. | FAB yield enhancement system |
US6507933B1 (en) * | 1999-07-12 | 2003-01-14 | Advanced Micro Devices, Inc. | Automatic defect source classification |
US6507800B1 (en) * | 2000-03-13 | 2003-01-14 | Promos Technologies, Inc. | Method for testing semiconductor wafers |
-
2000
- 2000-06-09 US US09/591,603 patent/US6701477B1/en not_active Expired - Lifetime
-
2001
- 2001-06-08 WO PCT/US2001/018732 patent/WO2001096835A2/en active Application Filing
- 2001-06-08 AU AU2001275454A patent/AU2001275454A1/en not_active Abandoned
Also Published As
Publication number | Publication date |
---|---|
WO2001096835A3 (en) | 2002-05-30 |
WO2001096835A8 (en) | 2002-02-21 |
WO2001096835A2 (en) | 2001-12-20 |
US6701477B1 (en) | 2004-03-02 |
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