AU2001263026A1 - Processor having selective branch prediction - Google Patents

Processor having selective branch prediction

Info

Publication number
AU2001263026A1
AU2001263026A1 AU2001263026A AU6302601A AU2001263026A1 AU 2001263026 A1 AU2001263026 A1 AU 2001263026A1 AU 2001263026 A AU2001263026 A AU 2001263026A AU 6302601 A AU6302601 A AU 6302601A AU 2001263026 A1 AU2001263026 A1 AU 2001263026A1
Authority
AU
Australia
Prior art keywords
processor
branch prediction
selective branch
selective
prediction
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
AU2001263026A
Other languages
English (en)
Inventor
William C. Moyer
Jeffrey W. Scott
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Motorola Solutions Inc
Original Assignee
Motorola Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Motorola Inc filed Critical Motorola Inc
Publication of AU2001263026A1 publication Critical patent/AU2001263026A1/en
Abandoned legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/32—Address formation of the next instruction, e.g. by incrementing the instruction counter
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/3005—Arrangements for executing specific machine instructions to perform operations for flow control
    • G06F9/30058—Conditional branch instructions
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3842—Speculative instruction execution
    • G06F9/3844—Speculative instruction execution using dynamic branch prediction, e.g. using branch history tables
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3842—Speculative instruction execution
    • G06F9/3846—Speculative instruction execution using static prediction, e.g. branch taken strategy

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Advance Control (AREA)
AU2001263026A 2000-06-12 2001-05-10 Processor having selective branch prediction Abandoned AU2001263026A1 (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US09592449 2000-06-12
US09/592,449 US6859875B1 (en) 2000-06-12 2000-06-12 Processor having selective branch prediction
PCT/US2001/015042 WO2001097021A1 (en) 2000-06-12 2001-05-10 Processor having selective branch prediction

Publications (1)

Publication Number Publication Date
AU2001263026A1 true AU2001263026A1 (en) 2001-12-24

Family

ID=24370679

Family Applications (1)

Application Number Title Priority Date Filing Date
AU2001263026A Abandoned AU2001263026A1 (en) 2000-06-12 2001-05-10 Processor having selective branch prediction

Country Status (7)

Country Link
US (1) US6859875B1 (ja)
EP (1) EP1295202A1 (ja)
JP (1) JP2004503865A (ja)
KR (1) KR100888356B1 (ja)
AU (1) AU2001263026A1 (ja)
TW (1) TW569139B (ja)
WO (1) WO2001097021A1 (ja)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100980076B1 (ko) 2003-10-24 2010-09-06 삼성전자주식회사 저전력 분기 예측 시스템 및 분기 예측 방법
KR100591769B1 (ko) * 2004-07-16 2006-06-26 삼성전자주식회사 분기 예측 정보를 가지는 분기 타겟 버퍼
US7725695B2 (en) * 2005-05-31 2010-05-25 Arm Limited Branch prediction apparatus for repurposing a branch to instruction set as a non-predicted branch
US7376807B2 (en) * 2006-02-23 2008-05-20 Freescale Semiconductor, Inc. Data processing system having address translation bypass and method therefor
US7401201B2 (en) * 2006-04-28 2008-07-15 Freescale Semiconductor, Inc. Processor and method for altering address translation
US20080040590A1 (en) * 2006-08-11 2008-02-14 Lea Hwang Lee Selective branch target buffer (btb) allocaiton
US20080040591A1 (en) * 2006-08-11 2008-02-14 Moyer William C Method for determining branch target buffer (btb) allocation for branch instructions
US8521996B2 (en) * 2009-02-12 2013-08-27 Via Technologies, Inc. Pipelined microprocessor with fast non-selective correct conditional branch instruction resolution
US8131984B2 (en) * 2009-02-12 2012-03-06 Via Technologies, Inc. Pipelined microprocessor with fast conditional branch instructions based on static serializing instruction state
KR102526610B1 (ko) * 2015-09-16 2023-04-28 엘지디스플레이 주식회사 메모리 제어장치 및 그 제어방법과 이를 포함한 유기발광 표시장치

Family Cites Families (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH081599B2 (ja) * 1988-02-24 1996-01-10 三菱電機株式会社 データ処理装置
JP2794768B2 (ja) * 1989-04-25 1998-09-10 スズキ株式会社 小型艇の操舵装置
JP2875909B2 (ja) * 1991-07-12 1999-03-31 三菱電機株式会社 並列演算処理装置
US5835967A (en) * 1993-10-18 1998-11-10 Cyrix Corporation Adjusting prefetch size based on source of prefetch address
TW261676B (ja) 1993-11-02 1995-11-01 Motorola Inc
IE940855A1 (en) 1993-12-20 1995-06-28 Motorola Inc Data processor with speculative instruction fetching and¹method of operation
JPH0893756A (ja) * 1994-09-20 1996-04-09 Ntn Corp 円筒ころ軸受
US5732253A (en) * 1994-10-18 1998-03-24 Cyrix Corporation Branch processing unit with target cache storing history for predicted taken branches and history cache storing history for predicted not-taken branches
US5996071A (en) * 1995-12-15 1999-11-30 Via-Cyrix, Inc. Detecting self-modifying code in a pipelined processor with branch processing by comparing latched store address to subsequent target address
US5701448A (en) * 1995-12-15 1997-12-23 Cyrix Corporation Detecting segment limit violations for branch target when the branch unit does not supply the linear address
US5752014A (en) * 1996-04-29 1998-05-12 International Business Machines Corporation Automatic selection of branch prediction methodology for subsequent branch instruction based on outcome of previous branch prediction
US5901307A (en) * 1996-07-22 1999-05-04 International Business Machines Corporation Processor having a selectively configurable branch prediction unit that can access a branch prediction utilizing bits derived from a plurality of sources
US5949995A (en) * 1996-08-02 1999-09-07 Freeman; Jackie Andrew Programmable branch prediction system and method for inserting prediction operation which is independent of execution of program code
US6088793A (en) * 1996-12-30 2000-07-11 Intel Corporation Method and apparatus for branch execution on a multiple-instruction-set-architecture microprocessor
US5951678A (en) 1997-07-25 1999-09-14 Motorola, Inc. Method and apparatus for controlling conditional branch execution in a data processor
JPH1185515A (ja) * 1997-09-10 1999-03-30 Ricoh Co Ltd マイクロプロセッサ
US6151672A (en) 1998-02-23 2000-11-21 Hewlett-Packard Company Methods and apparatus for reducing interference in a branch history table of a microprocessor
US6446197B1 (en) * 1999-10-01 2002-09-03 Hitachi, Ltd. Two modes for executing branch instructions of different lengths and use of branch control instruction and register set loaded with target instructions

Also Published As

Publication number Publication date
KR20030007952A (ko) 2003-01-23
EP1295202A1 (en) 2003-03-26
JP2004503865A (ja) 2004-02-05
TW569139B (en) 2004-01-01
US6859875B1 (en) 2005-02-22
WO2001097021A1 (en) 2001-12-20
KR100888356B1 (ko) 2009-03-11

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