AU2001257417A1 - Method and system for providing a flexible and efficient processor for use in graphics processing - Google Patents

Method and system for providing a flexible and efficient processor for use in graphics processing

Info

Publication number
AU2001257417A1
AU2001257417A1 AU2001257417A AU5741701A AU2001257417A1 AU 2001257417 A1 AU2001257417 A1 AU 2001257417A1 AU 2001257417 A AU2001257417 A AU 2001257417A AU 5741701 A AU5741701 A AU 5741701A AU 2001257417 A1 AU2001257417 A1 AU 2001257417A1
Authority
AU
Australia
Prior art keywords
flexible
providing
graphics processing
efficient processor
efficient
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
AU2001257417A
Other languages
English (en)
Inventor
Michael C. Lewis
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Broadcom Corp
Original Assignee
Broadcom Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Broadcom Corp filed Critical Broadcom Corp
Publication of AU2001257417A1 publication Critical patent/AU2001257417A1/en
Abandoned legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/57—Arithmetic logic units [ALU], i.e. arrangements or devices for performing two or more of the operations covered by groups G06F7/483 – G06F7/556 or for performing logical operations
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/30036—Instructions to perform operations on packed data, e.g. vector, tile or matrix operations
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3885—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3885—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units
    • G06F9/3887—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units controlled by a single instruction for multiple data lanes [SIMD]
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T1/00—General purpose image data processing
    • G06T1/20—Processor architectures; Processor configuration, e.g. pipelining

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Software Systems (AREA)
  • General Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Computational Mathematics (AREA)
  • Computing Systems (AREA)
  • Mathematical Analysis (AREA)
  • Mathematical Optimization (AREA)
  • Pure & Applied Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Image Generation (AREA)
  • Image Processing (AREA)
AU2001257417A 2000-05-01 2001-04-30 Method and system for providing a flexible and efficient processor for use in graphics processing Abandoned AU2001257417A1 (en)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US20103200P 2000-05-01 2000-05-01
US60201032 2000-05-01
US09590788 2000-06-08
US09/590,788 US6624819B1 (en) 2000-05-01 2000-06-08 Method and system for providing a flexible and efficient processor for use in a graphics processing system
PCT/US2001/013817 WO2001084297A2 (fr) 2000-05-01 2001-04-30 Procede et systeme permettant d'obtenir un processeur souple et efficace utilise dans un traitement graphique

Publications (1)

Publication Number Publication Date
AU2001257417A1 true AU2001257417A1 (en) 2001-11-12

Family

ID=26896318

Family Applications (1)

Application Number Title Priority Date Filing Date
AU2001257417A Abandoned AU2001257417A1 (en) 2000-05-01 2001-04-30 Method and system for providing a flexible and efficient processor for use in graphics processing

Country Status (4)

Country Link
US (2) US6624819B1 (fr)
EP (1) EP1281163A2 (fr)
AU (1) AU2001257417A1 (fr)
WO (1) WO2001084297A2 (fr)

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US6542998B1 (en) 1997-02-08 2003-04-01 Pact Gmbh Method of self-synchronization of configurable elements of a programmable module
US8686549B2 (en) * 2001-09-03 2014-04-01 Martin Vorbach Reconfigurable elements
DE19861088A1 (de) 1997-12-22 2000-02-10 Pact Inf Tech Gmbh Verfahren zur Reparatur von integrierten Schaltkreisen
EP1228440B1 (fr) 1999-06-10 2017-04-05 PACT XPP Technologies AG Partionnement de séquences dans des structures cellulaires
US6810432B1 (en) * 2000-04-03 2004-10-26 Hewlett-Packard Development Company, L.P. Method for guaranteeing a device minimun bandwidth on a usb bus
DE50115584D1 (de) 2000-06-13 2010-09-16 Krass Maren Pipeline ct-protokolle und -kommunikation
US8058899B2 (en) 2000-10-06 2011-11-15 Martin Vorbach Logic cell array and bus system
US7844796B2 (en) 2001-03-05 2010-11-30 Martin Vorbach Data processing device and method
US9037807B2 (en) 2001-03-05 2015-05-19 Pact Xpp Technologies Ag Processor arrangement on a chip including data processing, memory, and interface elements
US7444531B2 (en) 2001-03-05 2008-10-28 Pact Xpp Technologies Ag Methods and devices for treating and processing data
US7162716B2 (en) * 2001-06-08 2007-01-09 Nvidia Corporation Software emulator for optimizing application-programmable vertex processing
US7996827B2 (en) 2001-08-16 2011-08-09 Martin Vorbach Method for the translation of programs for reconfigurable architectures
US7434191B2 (en) 2001-09-03 2008-10-07 Pact Xpp Technologies Ag Router
US8686475B2 (en) 2001-09-19 2014-04-01 Pact Xpp Technologies Ag Reconfigurable elements
EP1483682A2 (fr) 2002-01-19 2004-12-08 PACT XPP Technologies AG Processeur reconfigurable
EP2043000B1 (fr) 2002-02-18 2011-12-21 Richter, Thomas Systèmes de bus et procédé de reconfiguration
US8914590B2 (en) 2002-08-07 2014-12-16 Pact Xpp Technologies Ag Data processing method and device
US7657861B2 (en) 2002-08-07 2010-02-02 Pact Xpp Technologies Ag Method and device for processing data
US20070083730A1 (en) * 2003-06-17 2007-04-12 Martin Vorbach Data processing device and method
WO2004021176A2 (fr) 2002-08-07 2004-03-11 Pact Xpp Technologies Ag Procede et dispositif de traitement de donnees
AU2003289844A1 (en) 2002-09-06 2004-05-13 Pact Xpp Technologies Ag Reconfigurable sequencer structure
US7987341B2 (en) * 2002-10-31 2011-07-26 Lockheed Martin Corporation Computing machine using software objects for transferring data that includes no destination information
JP4700611B2 (ja) 2003-08-28 2011-06-15 ペーアーツェーテー イクスペーペー テクノロジーズ アクチエンゲゼルシャフト データ処理装置およびデータ処理方法
US20060061577A1 (en) * 2004-09-22 2006-03-23 Vijay Subramaniam Efficient interface and assembler for a graphics processor
US20060230377A1 (en) * 2004-10-01 2006-10-12 Lockheed Martin Corporation Computer-based tool and method for designing an electronic circuit and related system
JP4425177B2 (ja) * 2005-05-20 2010-03-03 株式会社ソニー・コンピュータエンタテインメント グラフィックプロセッサ、情報処理装置
US8250503B2 (en) 2006-01-18 2012-08-21 Martin Vorbach Hardware definition method including determining whether to implement a function as hardware or software
KR20070092499A (ko) * 2006-03-10 2007-09-13 삼성전자주식회사 3차원 그래픽 데이터의 처리 방법 및 장치
US20100281235A1 (en) * 2007-11-17 2010-11-04 Martin Vorbach Reconfigurable floating-point and bit-level data processing unit
WO2011051756A1 (fr) * 2009-11-02 2011-05-05 Freescale Semiconductor, Inc. Appareil de traitement de données de pixels et procédé de traitement de données de pixels
JP2012252374A (ja) * 2011-05-31 2012-12-20 Renesas Electronics Corp 情報処理装置
US11481612B1 (en) * 2018-04-20 2022-10-25 Perceive Corporation Storage of input values across multiple cores of neural network inference circuit
CN115843268A (zh) 2020-04-17 2023-03-24 纽约大学 治疗性MuSK抗体
KR20220101518A (ko) * 2021-01-11 2022-07-19 에스케이하이닉스 주식회사 곱셈-누산 회로 및 이를 포함하는 프로세싱-인-메모리 장치

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JPS6297033A (ja) 1985-10-24 1987-05-06 Hitachi Ltd 乗算装置
US5187796A (en) 1988-03-29 1993-02-16 Computer Motion, Inc. Three-dimensional vector co-processor having I, J, and K register files and I, J, and K execution units
KR100280285B1 (ko) * 1996-08-19 2001-02-01 윤종용 멀티미디어 신호에 적합한 멀티미디어 프로세서
US6401194B1 (en) * 1997-01-28 2002-06-04 Samsung Electronics Co., Ltd. Execution unit for processing a data stream independently and in parallel
JPH1165989A (ja) * 1997-08-22 1999-03-09 Sony Computer Entertainment:Kk 情報処理装置
US6417858B1 (en) * 1998-12-23 2002-07-09 Microsoft Corporation Processor for geometry transformations and lighting calculations
US6417851B1 (en) * 1999-12-06 2002-07-09 Nvidia Corporation Method and apparatus for lighting module in a graphics processor

Also Published As

Publication number Publication date
US20040008201A1 (en) 2004-01-15
US6624819B1 (en) 2003-09-23
WO2001084297A3 (fr) 2002-06-13
WO2001084297A2 (fr) 2001-11-08
EP1281163A2 (fr) 2003-02-05

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