AU2001251107A1 - System for providing deterministic performance from a non-deterministic device - Google Patents

System for providing deterministic performance from a non-deterministic device

Info

Publication number
AU2001251107A1
AU2001251107A1 AU2001251107A AU5110701A AU2001251107A1 AU 2001251107 A1 AU2001251107 A1 AU 2001251107A1 AU 2001251107 A AU2001251107 A AU 2001251107A AU 5110701 A AU5110701 A AU 5110701A AU 2001251107 A1 AU2001251107 A1 AU 2001251107A1
Authority
AU
Australia
Prior art keywords
deterministic
providing
performance
deterministic performance
deterministic device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
AU2001251107A
Inventor
Glen D Stone
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sony Electronics Inc
Original Assignee
Sony Electronics Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Electronics Inc filed Critical Sony Electronics Inc
Publication of AU2001251107A1 publication Critical patent/AU2001251107A1/en
Abandoned legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system
    • G06F13/362—Handling requests for interconnection or transfer for access to common bus or bus system with centralised access control
    • G06F13/364—Handling requests for interconnection or transfer for access to common bus or bus system with centralised access control using independent requests or grants, e.g. using separated request and grant lines

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Information Transfer Systems (AREA)
AU2001251107A 2000-04-20 2001-03-29 System for providing deterministic performance from a non-deterministic device Abandoned AU2001251107A1 (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US09/553,304 US6438633B1 (en) 2000-04-20 2000-04-20 System for providing deterministic performance from a non-deterministic device
US09553304 2000-04-20
PCT/US2001/010145 WO2001082087A1 (en) 2000-04-20 2001-03-29 System for providing deterministic performance from a non-deterministic device

Publications (1)

Publication Number Publication Date
AU2001251107A1 true AU2001251107A1 (en) 2001-11-07

Family

ID=24208915

Family Applications (1)

Application Number Title Priority Date Filing Date
AU2001251107A Abandoned AU2001251107A1 (en) 2000-04-20 2001-03-29 System for providing deterministic performance from a non-deterministic device

Country Status (3)

Country Link
US (1) US6438633B1 (en)
AU (1) AU2001251107A1 (en)
WO (1) WO2001082087A1 (en)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6578109B1 (en) * 2000-06-29 2003-06-10 Sony Corporation System and method for effectively implementing isochronous processor cache
WO2003034194A1 (en) * 2001-09-19 2003-04-24 Thomson Licensing S.A. Programmable bandwidth limiter using handshake suppression
US7720639B2 (en) * 2005-10-27 2010-05-18 General Electric Company Automatic remote monitoring and diagnostics system and communication method for communicating between a programmable logic controller and a central unit
US8259576B2 (en) * 2007-03-23 2012-09-04 Intel Corporation Method and apparatus for performing interrupt coalescing

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5953511A (en) * 1997-04-08 1999-09-14 National Instruments Corporation PCI bus to IEEE 1394 bus translator
US6115770A (en) * 1998-03-25 2000-09-05 Lsi Logic Corporation System and method for coordinating competing register accesses by multiple buses
US6243778B1 (en) * 1998-10-13 2001-06-05 Stmicroelectronics, Inc. Transaction interface for a data communication system
US6169745B1 (en) * 1999-06-18 2001-01-02 Sony Corporation System and method for multi-level context switching in an electronic network

Also Published As

Publication number Publication date
US6438633B1 (en) 2002-08-20
WO2001082087A1 (en) 2001-11-01

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