AU2001232023A1 - Method and apparatus for binary encoding logic circuits - Google Patents

Method and apparatus for binary encoding logic circuits

Info

Publication number
AU2001232023A1
AU2001232023A1 AU2001232023A AU3202301A AU2001232023A1 AU 2001232023 A1 AU2001232023 A1 AU 2001232023A1 AU 2001232023 A AU2001232023 A AU 2001232023A AU 3202301 A AU3202301 A AU 3202301A AU 2001232023 A1 AU2001232023 A1 AU 2001232023A1
Authority
AU
Australia
Prior art keywords
logic circuits
binary encoding
encoding logic
binary
circuits
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
AU2001232023A
Other languages
English (en)
Inventor
Peter Meulemans
Talwar Sunil
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Automatic Parallel Designs Ltd
Original Assignee
Automatic Parallel Designs Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Automatic Parallel Designs Ltd filed Critical Automatic Parallel Designs Ltd
Publication of AU2001232023A1 publication Critical patent/AU2001232023A1/en
Abandoned legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Evolutionary Computation (AREA)
  • Geometry (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Compression, Expansion, Code Conversion, And Decoders (AREA)
  • Error Detection And Correction (AREA)
AU2001232023A 2000-01-27 2001-01-29 Method and apparatus for binary encoding logic circuits Abandoned AU2001232023A1 (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
GB0001916A GB2358719B (en) 2000-01-27 2000-01-27 Method and apparatus for binary encoding logic circuits
GB0001916.6 2000-01-27
PCT/GB2001/000497 WO2001055916A2 (fr) 2000-01-27 2001-01-29 Procede et dispositif de codage binaire de circuits logiques

Publications (1)

Publication Number Publication Date
AU2001232023A1 true AU2001232023A1 (en) 2001-08-07

Family

ID=9884477

Family Applications (1)

Application Number Title Priority Date Filing Date
AU2001232023A Abandoned AU2001232023A1 (en) 2000-01-27 2001-01-29 Method and apparatus for binary encoding logic circuits

Country Status (5)

Country Link
US (1) US6628215B2 (fr)
EP (1) EP1275063A2 (fr)
AU (1) AU2001232023A1 (fr)
GB (3) GB2358719B (fr)
WO (1) WO2001055916A2 (fr)

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US6829695B1 (en) * 1999-09-03 2004-12-07 Nexql, L.L.C. Enhanced boolean processor with parallel input
US20040225865A1 (en) * 1999-09-03 2004-11-11 Cox Richard D. Integrated database indexing system
AU2003231112A1 (en) * 2002-04-26 2003-11-10 California Institute Of Technology System and method for clockless data recovery
US7020865B2 (en) 2003-06-24 2006-03-28 Lsi Logic Corporation Process for designing comparators and adders of small depth
US7307453B1 (en) * 2004-10-12 2007-12-11 Nortel Networks Limited Method and system for parallel state machine implementation
US7242329B2 (en) * 2005-02-02 2007-07-10 Gm Global Technology Operations, Inc. Method and system for prioritizing data values for robust data representation
US7895560B2 (en) * 2006-10-02 2011-02-22 William Stuart Lovell Continuous flow instant logic binary circuitry actively structured by code-generated pass transistor interconnects
US7538697B1 (en) * 2008-02-27 2009-05-26 Red Hat, Inc. Heuristic modeling of adaptive compression escape sequence
FR2933514B1 (fr) * 2008-07-02 2012-10-19 Canon Kk Procedes et dispositifs de codage et de decodage par similarites pour documents de type xml
US8044787B2 (en) * 2008-10-07 2011-10-25 Eaton Corporation Discrete sensor inputs
WO2015165037A1 (fr) * 2014-04-29 2015-11-05 中国科学院自动化研究所 Procédé d'appariement d'images à base de codage binaire en cascade
US20160350668A1 (en) * 2015-06-01 2016-12-01 Assurant Design Automation LLC Risk evaluation
US10402175B2 (en) 2015-06-01 2019-09-03 Assurant Design Automation LLC Parsing source code into a linear array
US9590858B2 (en) 2015-06-01 2017-03-07 Assurant Design Automation LLC Identifying a nearest connection
US10747919B2 (en) 2015-06-01 2020-08-18 Assurant Design Automation LLC Generating path execution times
US10997335B2 (en) 2015-06-01 2021-05-04 Assurant Design Automation LLC Exceptional logic element management
US9396298B1 (en) * 2015-06-01 2016-07-19 Assurant Design Automation LLC Linear array display
US9536029B2 (en) 2015-06-01 2017-01-03 Assurant Design Automation LLC Linear array hierarchy navigation
US11610038B2 (en) * 2015-06-01 2023-03-21 Assurant Design Automation LLC Risk evaluation
US10997334B2 (en) 2015-06-01 2021-05-04 Assurant Design Automation LLC Implementing a logic design
US10678980B2 (en) 2015-06-01 2020-06-09 Assurant Design Automation LLC Combination map based composite design
US9535665B2 (en) 2015-06-01 2017-01-03 Assurant Design Automation LLC Hardware/software agnostic design generation

Family Cites Families (7)

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Publication number Priority date Publication date Assignee Title
US4463344A (en) * 1981-12-31 1984-07-31 International Business Machines Corporation Method and apparatus for generating a noiseless sliding block code for a (2,7) channel with rate 1/2
US5272478A (en) * 1992-08-17 1993-12-21 Ricoh Corporation Method and apparatus for entropy coding
US5475388A (en) * 1992-08-17 1995-12-12 Ricoh Corporation Method and apparatus for using finite state machines to perform channel modulation and error correction and entropy coding
US5515292A (en) * 1993-09-29 1996-05-07 Texas Instruments Incorporated Circuit activity driven state assignment of FSMS implemented in CMOS for low power reliable operations
TW298687B (fr) * 1995-04-21 1997-02-21 Hitachi Ltd
US6173414B1 (en) * 1998-05-12 2001-01-09 Mcdonnell Douglas Corporation Systems and methods for reduced error detection latency using encoded data
US6216260B1 (en) * 1999-02-01 2001-04-10 Anna Alshansky Method for automatic synthesis of a digital circuit employing an algorithm flowchart

Also Published As

Publication number Publication date
WO2001055916A3 (fr) 2002-10-24
WO2001055916A2 (fr) 2001-08-02
GB0402264D0 (en) 2004-03-10
GB2395823B (en) 2004-08-25
EP1275063A2 (fr) 2003-01-15
GB0402265D0 (en) 2004-03-10
GB2397672B (en) 2004-09-22
GB0001916D0 (en) 2000-03-22
GB2358719B (en) 2004-05-05
GB2395823A (en) 2004-06-02
GB2397672A (en) 2004-07-28
US6628215B2 (en) 2003-09-30
US20010044708A1 (en) 2001-11-22
GB2358719A (en) 2001-08-01

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