US5515292A - Circuit activity driven state assignment of FSMS implemented in CMOS for low power reliable operations - Google Patents
Circuit activity driven state assignment of FSMS implemented in CMOS for low power reliable operations Download PDFInfo
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- US5515292A US5515292A US08/129,816 US12981693A US5515292A US 5515292 A US5515292 A US 5515292A US 12981693 A US12981693 A US 12981693A US 5515292 A US5515292 A US 5515292A
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- G06F2119/00—Details relating to the type or aim of the analysis or the optimisation
- G06F2119/06—Power analysis or power optimisation
Definitions
- This invention generally relates to finite state machine (FSM) synthesis and more specifically to circuit activity driven state assignment of FSMs for low power reliable operations.
- FSM finite state machine
- Finite state machine (FSM) and combinational logic synthesis have been conventionally targeted to reducing the area and the critical path delay. Recently, testability has also been considered.
- power dissipation considerations have received little attention.
- the minimization of power in CMOS circuits is of extreme importance, especially for portable operations.
- Power dissipation in CMOS circuits has traditionally been minimized by scaling down the supply voltage.
- the supply voltage is scaled down, the circuit performance becomes slower.
- the slower performance can be compensated for by using scaled down device features, but several other effects such as dominant interconnect capacitance becomes very important. Accordingly, there is a need for FSM synthesis that also minimizes power dissipation.
- a method for optimizing a circuit containing a finite state machine is disclosed. The method is based on the concept of choosing a state assignment for each state of the FSM such that transition density is minimized.
- a first state assignment is assigned for each state.
- a first transition density characteristic associated with the first state assignment is determined and a second state assignment, different from said first state assignment is assigned for each state.
- a second transition density characteristic associated with the second state assignment is then determined and the first state assignment is set equal to the second state assignment if second transition density characteristic is less than a predetermined amount. The process is repeated until the transition density has been minimized.
- An advantage of the invention is providing FSM synthesis that minimizes power dissipation.
- Another advantage of the invention is providing FSM synthesis that minimizes transition density.
- FIG. 1 is a generic block diagram of circuits that may be optimized according to the preferred embodiment of the invention
- FIG. 2 is a Probabilistic State Transition Graph of a set of nodes to be optimized according to the preferred embodiment of the invention
- FIG. 3 is a block diagram showing the propagation of transition densities through basic circuit gates
- FIG. 4 is a flow diagram of the preferred embodiment of the invention.
- FIG. 5 is an example state machine on which the preferred embodiment of the invention may be practiced
- FIG. 5a is a table of coding examples for the state machine of FIG. 5.
- FIG. 6 is a graph of a spice simulation showing the results of optimization according to the preferred embodiment of the invention.
- CMOS circuit power is dissipated only when there is a transition (a ZERO to ONE or ONE to ZERO in logic value) at the output of a gate and is given by ##EQU1## where C is the capacitive bad and f denotes the frequency of operation with a supply voltage of V DD .
- f can be expressed in terms of ##EQU2## where n x is the number of transitions at node x in time ##EQU3## Frequency, f in this situation is defined as transition density. Transition density is a measure of the average switching rate at any node of a circuit.
- transition densities at any node of a multilevel circuit can be obtained by logic simulation.
- the rate at which node transition occurs is also a measure of the stress that can cause failures in digital circuits.
- the circuits synthesized using transition density measure are less susceptible to run time failures.
- the synthesis process of the preferential embodiment consists of two parts: state assignment which determines the combinational logic function, and multilevel optimization of the combinational logic based on transition density measure.
- the state assignment scheme considers the likelihood of state transitions--the probability of a state transition (from state S 1 to state S 2 ) when the primary input signal probabilities are given. An input signal probability is given by the fraction of time a logical ONE appears at that input.
- the state assignment minimizes the total number of transitions occurring at the v inputs (or the present state inputs) of the state machine shown in FIG. 1.
- Multilevel combinational logic is synthesized from two-level expressions by a factorization scheme which tries to minimize area while at the same time trying to reduce the transition densities at the internal nodes of the circuit.
- the optimization process is iterative. During each iteration, the best sub-expression from among all promising common sub-expressions, is selected. The activity number is based on both area and power savings. The selected sub-expression is factored out of all affected expressions. The iteration is continued until no further savings can be realized.
- the synthesis technique can handle input signal probabilities and transition densities, and hence, a particular circuit can be optimally synthesized in different ways suited for different applications requiring different types of inputs.
- FSMs Finite state machines
- PSTGs Probabilistic State Transition Graphs
- a PSTG is shown in FIG. 2.
- PSTGs are directed graphs consisting of a set of nodes S and a set of edges E.
- Each node S i ⁇ S represents a state of the FSM.
- each edge is associated with a label L ij which carries information on the values of primary inputs that caused the transition and the value of the primary outputs corresponding to the state transition.
- Each edge is also associated with a number p ij , 0 ⁇ p ij ⁇ 1, which denotes the conditional probability of a state transition from state S i to S j , given that the state machine is at state S i , and is directly related to the signal probabilities of the primary input nodes.
- the cardinality of set S, N s gives the total number of states in the machine.
- the number of primary inputs and primary outputs are denoted by N I and N O respectively.
- Completely specified FSMs are used.
- the state assignment problem involves assigning unique Boolean numbers of same length to different states of an FSM so as to satisfy some given criteria. Given a state assignment, the Hamming distance between any two states S i and S j is given by
- H(S i , S j ) denotes the total number of bits that states S i and S j differ in. For example, if S 1 was assigned the value "010" and S 2 was assigned the value "011", H(S 1 ,S 2 ) would equal 1.
- the signal probability of signal g is given by: ##EQU5##
- P(g) is a measure of the probability that signal g assumes a logic value of ONE.
- transition density is formally defined as follows: ##EQU6## where n g (t) is the number of transitions of g(t) in the time interval between ##EQU7## D(g) has the unit of the number of transitions per unit time. Transition density is a measure of activity in a digital circuit. Therefore, it is related to reliability. Hence, the circuits realized to reduce transition density measure may be more reliable.
- Logic module M is a multi-input, multi-output logic module which implements a Boolean function.
- M can be a single logic gate or a higher level circuit block.
- the inputs to M, g 1 , g 2 , . . . g n are mutually independent companion processes each having a signal probability of P(g i ), and a transition density of D(g i ), i ⁇ n.
- the signal probability at the output can be easily computed using methods well known in the art.
- FIG. 3 shows the propagation of transition density through AND, OR, and NOT gates.
- the signal probabilities and the transition densities at the primary inputs to a circuit are usually available.
- the state encoding scheme uses the likelihood of state transition information. Accordingly, the state transition probability, P ij , for each possible state transition must be determined (Step 1).
- the likelihood of state transition from state S 1 to S 2 is the maximum.
- p ij and L ij respectively denote the conditional state transition probability (given that the FSM is in state S i ,p ij is the probability that the next state is S j ) and the label associated with an edge S i -S j of a PSTG with N I primary inputs each having a signal probability of P x ,x ⁇ N I .
- Each primary input x in L ij which causes the state transition to occur, can assume a logic value value(x), from the set ⁇ 1,0,- ⁇ , where ⁇ - ⁇ represents the don't care condition.
- N s states the minimum number of flip-flops required for coding is log 2 N s !. It should be noted that if one-hot coding with N s flip-flops are used, the Hamming distance between any two states are always 2, and hence, an optimum assignment to minimize the number of switching at the present state inputs might not be obtainable. Be sides, one-hot coding also increases the number of present state inputs to the combinational logic of FIG. 1. The average number of switching at the present state inputs to a state machine can be minimized if the state assignment scheme is such that the following activity number is minimized: ##EQU12## The above function represents the summation of all Hamming distances between two adjacent states weighted by the state transition probability. The higher the state transition probability between two states, the lower should be the Hamming distance between those two states.
- Step 2 a random assignment of states with the prescribed number of bits is chosen (Step 2).
- the activity number ⁇ may be determined for the random assignment (Step 3).
- Two types of moves are allowed during annealing to create a new assignment possibility (Step 4): interchange the codes of two states, or assign an unassigned code to the state which is randomly picked for exchange.
- the activity number ⁇ may then be determined for the new assignment possibility (Step 5).
- the move is accepted (Step 6) if the new assignment decreases ⁇ .
- FIG. 5 shows a state machine which produces an output of ONE whenever a sequence of five ONEs appear, else it outputs a ZERO.
- the machine was implemented using three D type flip-flops using the two assignment schemes shown in the table.
- the input signal probability is assumed to be 0.5, and hence, each edge of the state transition graph has a state transition probability of 0.5.
- For Coding 1, ⁇ , is 10, whereas, for Coding 2, ⁇ is 5.5.
- the machines can be implemented using 34 transistors and 3 flip-flops and 36 transistors and 3 flip-flops respectively.
- SPICE with random inputs show that the time average power dissipated with the first encoding is more than the second one.
- State assignment determines the functionality of combinational logic.
- the combinational logic is represented by F(I, V), where I is the set of primary inputs, and V represents the present state inputs (refer to FIG. 1).
- the signal probabilities and transition densities are given for each input i k ⁇ I.
- the signal probabilities and transition densities for the V inputs have to be determined in order to synthesize multi-level combinational logic based on power dissipation measure.
- the V inputs are the same as U outputs, but delayed by a clock period.
- the signal probabilities and the transition densities of V inputs are equal to the corresponding values for the U outputs.
- the state machine is simulated with different inputs to determine the signal probabilities and transition densities at the present state inputs.
- the simulation proceeds as follows. Primary input signals are randomly generated such that the signal probabilities and transition densities conform to given distribution.
- the state machine is simulated to determine the percentage of time bit v j of the state machine has a logical value of ONE. Similarly, the number of transitions occurring at bit v j of the machine is also determined. The number of transitions divided by the total number of simulations gives transition density at input D(v j ). The unit of D(v j ) is transitions per clock period.
- the simulations can be carried out very fast because of the way the primary input signals are generated.
- the multi-level combinational logic is synthesized.
- the multilevel logic is optimized for both area and power as described in co-pending U.S. patent application Ser. No. 08/018,984 filed Feb. 18, 1993, assigned to TI and hereby incorporated by reference.
- the combinational logic synthesis finds multiple cube common divisors or single cube common divisors among two or more nodes.
- a set of kernels are computed for each logic expression. Then the non-trivial intersection among kernels from different functions are formed. While choosing the best intersection, both the reduction in literal count and the reduction in power dissipation measure ⁇ that will occur if we choose that factor are considered.
- Both level 0 and higher level kernels are generated. The best N kernel intersections on the basis of literal count reduction are chosen, and among them the one which gives the best trade-off between area and power reduction is selected.
- the reduction in the power dissipation measure ⁇ is also calculated.
- the best factor is chosen by using a saving function S.
- S For the calculation of the reduction in ⁇ , one implementation would involve putting the factor as a node in the network, subsequently dividing all the nodes for which this new node can be a factor, then calculating ⁇ , and finally removing the node from the network along with all its effect on the network.
- Choosing the best factor out of N choices using the above method may be expensive from computational point of view.
- the power dissipation due to transitions at circuit node local to the factor under consideration are computed. This value is used to compute a power savings ⁇ similar to the area savings ⁇ A.
- the synthesis problem is broken up into two parts--the state assignment problem where the activity number ⁇ is minimized so as to reduce the transition densities at the present state inputs V, and the multilevel combinational logic synthesis proc2ess based on power dissipation measure and area.
- the state assignment and the subsequent logic synthesis process can get greatly affected if the primary input signal probabilities and transition densities are altered.
- Table 1 shows the results of the state assignment scheme according to the preferred embodiment on the MCNC benchmark examples.
- the number of states, primary inputs, primary outputs, and the number of edges in the state transition graph are shown in the Table.
- For all primary inputs a signal probability of 0.5 and a transition density of 0.5 transition per clock cycle were assumed. It should be noted that a different state assignment will be obtained if the input signal probabilities are changed.
- the state machines were experimented with the .left brkt-top.log 2 S.right brkt-top. state bits, which is the minimum number of bits required to code the state machine.
- the signal probabilities and transition densities at the V inputs to the combinational logic to be used in the multilevel synthesis are determined after state assignment using simulation. 10,000 randomly generated primary inputs (conforming to a given distribution) were simulated. Table 2 shows the results of applying the synthesis algorithm or the preferred embodiment to the MCNC benchmark examples of Table 1. Two types of circuits were synthesized for comparisons. The second and the third column shows the transistor count and the power dissipation measure ⁇ of the circuits synthesized using the state encoding scheme which produces an activity number of ⁇ min . Similar results for circuits encoded with states which produced ⁇ max as activity number are shown next for comparison. In both cases, the combinational logic was synthesized to minimize power dissipation measure.
- FIG. 5 The example state machine of FIG. 5 which outputs a ONE only when a sequence of five ONES appear at the input was synthesized using the two encodings shown in the Figure. Input signal probability of 0.5 and a transition density of 0.5 transitions per unit clock period was assumed. With the same inputs, and 0.8 micron technology the two machines were simulated with 1000 inputs using SPICE. FIG. 6 shows time average power for the two machines. Coding 1 for which ⁇ is higher produced more power dissipation than the one with lower ⁇ .
- the synthesis system of the preferred embodiment has been developed to synthesize both finite state machines and combinational logic for low power applications. It tries to minimize the transition density at the internal nodes of a circuit to minimize power dissipation during normal operation.
- a particular circuit can be synthesized in different ways for different applications which require different types of inputs.
- simulation was used to determine the signal probabilities and transition densities. log 2 S! number of bits were used for state assignment.
- the invention is not limited by the number of bits used for state assignment.
- the multilevel optimization process extracts kernels such that there is a balance between area and power optimization.
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Description
H(S.sub.i, S.sub.j)=J(S.sub.i ⊕S.sub.j)
B(y,x)==y|.sub.x=0 ⊕y|.sub.x=1 =y(x)⊕y(.sub.x.sup.-)
TABLE 1 ______________________________________ Results on benchmark examples with minimum coding bits example states input output edges γmin γmax ______________________________________ ex1 20 9 19 138 25.5 40.03 ex3 10 2 2 36 16.25 23.25 ex7 10 2 2 36 13.75 21.75 keyb 19 7 2 170 68.1 145.8 sand 32 11 9 184 37.48 57.65 train11 11 2 1 25 5.5 10.75 opus 10 5 6 22 6.59 13.15bbtas 6 2 2 24 3.5 8.75 lion9 9 2 1 25 5.0 12.0 bbara 10 4 2 60 3.5 5.8 planet 48 7 19 115 110.81 172.875 ______________________________________
TABLE 2 ______________________________________ Synthesis Results γmin γmax example transistors Φ transistors Φ ______________________________________ ex1 2072 984.4 2380 1465.2 ex3 284 46.4 344 55.3 ex7 304 48.8 404 62.8 keyb 1364 561.4 2424 1170.4 sand 2958 1497.1 3040 1503.4 train11 418 101.3 466 151.3 opus 452 160.1 530 234.2 bbtas 90 20.2 130 55.2 lion9 276 66.9 374 131.1 bbara 290 69.0 342 105.4 planet 2650 2012.0 3226 3854.9 ______________________________________
Claims (14)
H(S.sub.i,S.sub.j)=J(S.sub.i ⊕S.sub.j)
γ.sub.1 =Σ p.sub.ij H(S.sub.i,S.sub.j)
γ.sub.2 =Σ p.sub.ij H(S.sub.i,S.sub.j)
H(S.sub.i,S.sub.j)=J(S.sub.i ⊕S.sub.j)
γ.sub.1 =Σ p.sub.ij H(S.sub.i,S.sub.j)
γ.sub.2 =Σ p.sub.ij H(S.sub.i,S.sub.j)
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Cited By (18)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5706205A (en) * | 1994-09-30 | 1998-01-06 | Kabushiki Kaisha Toshiba | Apparatus and method for high-level synthesis of a logic circuit |
US5805459A (en) * | 1995-04-24 | 1998-09-08 | Texas Instruments Incorporated | Method of measuring activity in a digital circuit |
US5825644A (en) * | 1996-03-04 | 1998-10-20 | Motorola, Inc. | Method for encoding a state machine |
US6028988A (en) * | 1996-11-11 | 2000-02-22 | Nec Corporation | System for logic synthesis-for-testability capable of improving testability for an FSM having an asynchronous reset state |
US6070258A (en) * | 1997-03-07 | 2000-05-30 | Nec Corporation | Logic synthesis for testability system which enables improvement in testability and effective selection of center state and logic synthesis method thereof |
US6075932A (en) * | 1994-06-03 | 2000-06-13 | Synopsys, Inc. | Method and apparatus for estimating internal power consumption of an electronic circuit represented as netlist |
US6442741B1 (en) * | 2000-10-06 | 2002-08-27 | Lsi Logic Corporation | Method of automatically generating schematic and waveform diagrams for analysis of timing margins and signal skews of relevant logic cells using input signal predictors and transition times |
US6628215B2 (en) * | 2000-01-27 | 2003-09-30 | Automatic Parallel Design Limited | Method and apparatus for binary encoding logic circuits |
US20040083011A1 (en) * | 2002-10-21 | 2004-04-29 | Abb Schweiz Ag | Finite state machine display for operator guidance |
US20040139416A1 (en) * | 2002-12-05 | 2004-07-15 | Riedel Marcus D. | Synthesis of cyclic combinational circuits |
US6816827B1 (en) * | 1999-10-01 | 2004-11-09 | Nec Corporation | Verification method for combinational loop systems |
US20050037040A1 (en) * | 2003-08-13 | 2005-02-17 | Moshe Arkin | Topical compositions of urea and ammonium lactate |
US20060253816A1 (en) * | 2004-03-12 | 2006-11-09 | Sensory Networks, Inc. | Apparatus and Method For Memory Efficient, Programmable, Pattern Matching Finite State Machine Hardware |
US20060290378A1 (en) * | 2005-06-10 | 2006-12-28 | Azuro (Uk) Limited | Estimation of average-case activity for digital state machines |
US20060291126A1 (en) * | 2005-06-10 | 2006-12-28 | Azuro (Uk) Limited | Estimation of average-case activity for circuit elements in a digital circuit |
US20090192781A1 (en) * | 2008-01-30 | 2009-07-30 | At&T Labs | System and method of providing machine translation from a source language to a target language |
US20090319842A1 (en) * | 2006-09-27 | 2009-12-24 | Japan Science And Technology Agency | Generating device, generating method, program and recording medium |
US10042965B2 (en) | 2016-07-21 | 2018-08-07 | King Fahd University Of Petroleum And Minerals | Systems and method for optimizing state encoding |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5097151A (en) * | 1990-02-16 | 1992-03-17 | U.S. Philips Corporation | Sequential finite-state machine circuit and integrated circuit |
US5317757A (en) * | 1992-02-06 | 1994-05-31 | International Business Machines Corporation | System and method for finite state machine processing using action vectors |
-
1993
- 1993-09-29 US US08/129,816 patent/US5515292A/en not_active Expired - Lifetime
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5097151A (en) * | 1990-02-16 | 1992-03-17 | U.S. Philips Corporation | Sequential finite-state machine circuit and integrated circuit |
US5317757A (en) * | 1992-02-06 | 1994-05-31 | International Business Machines Corporation | System and method for finite state machine processing using action vectors |
Non-Patent Citations (12)
Title |
---|
Ghosh et al., "Estimation of Average Switching Activity in Combinational and Sequential Circuits", IEEE 1992, pp. 253-259. |
Ghosh et al., Estimation of Average Switching Activity in Combinational and Sequential Circuits , IEEE 1992, pp. 253 259. * |
Kaushik Roy and Sharat Prasad, "SYCLOP: Synthesis of CMOS Logig for Low Power Applications", International Conference on Computer Design, Boston, Oct. 11-14, 1992. |
Kaushik Roy and Sharat Prasad, SYCLOP: Synthesis of CMOS Logig for Low Power Applications , International Conference on Computer Design, Boston, Oct. 11 14, 1992. * |
Nagj, "Transition Density: A Now Measure of Activity in Digital Circuit", IEEE 1992, pp. 310-323. |
Nagj, Transition Density: A Now Measure of Activity in Digital Circuit , IEEE 1992, pp. 310 323. * |
Pasbt et al., "Experiments on the Synthesis and Testability of Non-Scan Finite State Machines", IEEE 1992, pp. 537-542. |
Pasbt et al., Experiments on the Synthesis and Testability of Non Scan Finite State Machines , IEEE 1992, pp. 537 542. * |
Srinivas Devadas, et al., "Mustang: State Assignment of Finite State Machines Targeting Multilevel Logic Implementations", IEEE Trans on Computer Aided Design, vol. 7, No. 12, Dec. 1988, pp. 1290-1300. |
Srinivas Devadas, et al., Mustang: State Assignment of Finite State Machines Targeting Multilevel Logic Implementations , IEEE Trans on Computer Aided Design, vol. 7, No. 12, Dec. 1988, pp. 1290 1300. * |
Villa et al., "Nova: State Assignment of Finite State Machines for Optimal Two-level Logic Implementation", IEEE 1990, pp. 905-924. |
Villa et al., Nova: State Assignment of Finite State Machines for Optimal Two level Logic Implementation , IEEE 1990, pp. 905 924. * |
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US6075932A (en) * | 1994-06-03 | 2000-06-13 | Synopsys, Inc. | Method and apparatus for estimating internal power consumption of an electronic circuit represented as netlist |
US5706205A (en) * | 1994-09-30 | 1998-01-06 | Kabushiki Kaisha Toshiba | Apparatus and method for high-level synthesis of a logic circuit |
US5805459A (en) * | 1995-04-24 | 1998-09-08 | Texas Instruments Incorporated | Method of measuring activity in a digital circuit |
US5825644A (en) * | 1996-03-04 | 1998-10-20 | Motorola, Inc. | Method for encoding a state machine |
US6028988A (en) * | 1996-11-11 | 2000-02-22 | Nec Corporation | System for logic synthesis-for-testability capable of improving testability for an FSM having an asynchronous reset state |
US6070258A (en) * | 1997-03-07 | 2000-05-30 | Nec Corporation | Logic synthesis for testability system which enables improvement in testability and effective selection of center state and logic synthesis method thereof |
US6816827B1 (en) * | 1999-10-01 | 2004-11-09 | Nec Corporation | Verification method for combinational loop systems |
US6628215B2 (en) * | 2000-01-27 | 2003-09-30 | Automatic Parallel Design Limited | Method and apparatus for binary encoding logic circuits |
US6442741B1 (en) * | 2000-10-06 | 2002-08-27 | Lsi Logic Corporation | Method of automatically generating schematic and waveform diagrams for analysis of timing margins and signal skews of relevant logic cells using input signal predictors and transition times |
US20040083011A1 (en) * | 2002-10-21 | 2004-04-29 | Abb Schweiz Ag | Finite state machine display for operator guidance |
US20040139416A1 (en) * | 2002-12-05 | 2004-07-15 | Riedel Marcus D. | Synthesis of cyclic combinational circuits |
US7249341B2 (en) * | 2002-12-05 | 2007-07-24 | California Institute Of Technology | Synthesis of cyclic combinational circuits |
US20050037040A1 (en) * | 2003-08-13 | 2005-02-17 | Moshe Arkin | Topical compositions of urea and ammonium lactate |
US20060253816A1 (en) * | 2004-03-12 | 2006-11-09 | Sensory Networks, Inc. | Apparatus and Method For Memory Efficient, Programmable, Pattern Matching Finite State Machine Hardware |
US7219319B2 (en) * | 2004-03-12 | 2007-05-15 | Sensory Networks, Inc. | Apparatus and method for generating state transition rules for memory efficient programmable pattern matching finite state machine hardware |
US20060291126A1 (en) * | 2005-06-10 | 2006-12-28 | Azuro (Uk) Limited | Estimation of average-case activity for circuit elements in a digital circuit |
US7222039B2 (en) * | 2005-06-10 | 2007-05-22 | Azuro (Uk) Limited | Estimation of average-case activity for digital state machines |
US20060290378A1 (en) * | 2005-06-10 | 2006-12-28 | Azuro (Uk) Limited | Estimation of average-case activity for digital state machines |
US7630851B2 (en) * | 2005-06-10 | 2009-12-08 | Azuro (Uk) Limited | Estimation of average-case activity for circuit elements in a digital circuit |
US20090319842A1 (en) * | 2006-09-27 | 2009-12-24 | Japan Science And Technology Agency | Generating device, generating method, program and recording medium |
US7979765B2 (en) * | 2006-09-27 | 2011-07-12 | Japan Science & Technology Agency | Generating device, generating method, program and recording medium |
US20090192781A1 (en) * | 2008-01-30 | 2009-07-30 | At&T Labs | System and method of providing machine translation from a source language to a target language |
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US10042965B2 (en) | 2016-07-21 | 2018-08-07 | King Fahd University Of Petroleum And Minerals | Systems and method for optimizing state encoding |
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US10169512B2 (en) * | 2016-07-21 | 2019-01-01 | King Fahd University Of Petroleum And Minerals | Computer system for state assignments using a finite state machine |
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