AU2001212724A1 - Multiplier and shift device using signed digit representation - Google Patents

Multiplier and shift device using signed digit representation

Info

Publication number
AU2001212724A1
AU2001212724A1 AU2001212724A AU1272401A AU2001212724A1 AU 2001212724 A1 AU2001212724 A1 AU 2001212724A1 AU 2001212724 A AU2001212724 A AU 2001212724A AU 1272401 A AU1272401 A AU 1272401A AU 2001212724 A1 AU2001212724 A1 AU 2001212724A1
Authority
AU
Australia
Prior art keywords
reduced
shifting
hardware
multiplication
multiplier
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
AU2001212724A
Inventor
Kari Halonen
Marko Kosunen
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nokia Oyj
Original Assignee
Nokia Oyj
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nokia Oyj filed Critical Nokia Oyj
Publication of AU2001212724A1 publication Critical patent/AU2001212724A1/en
Abandoned legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/52—Multiplying; Dividing
    • G06F7/523—Multiplying only
    • G06F7/527—Multiplying only in serial-parallel fashion, i.e. one operand being entered serially and the other in parallel
    • G06F7/5272—Multiplying only in serial-parallel fashion, i.e. one operand being entered serially and the other in parallel with row wise addition of partial products
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F5/00—Methods or arrangements for data conversion without changing the order or content of the data handled
    • G06F5/01—Methods or arrangements for data conversion without changing the order or content of the data handled for shifting, e.g. justifying, scaling, normalising
    • G06F5/015—Methods or arrangements for data conversion without changing the order or content of the data handled for shifting, e.g. justifying, scaling, normalising having at least two separately controlled shifting levels, e.g. using shifting matrices
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/52—Multiplying; Dividing
    • G06F7/523—Multiplying only
    • G06F7/533—Reduction of the number of iteration steps or stages, e.g. using the Booth algorithm, log-sum, odd-even
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/3001—Arithmetic instructions
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/30025—Format conversion instructions, e.g. Floating-Point to Integer, decimal conversion

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Pure & Applied Mathematics (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Optimization (AREA)
  • Mathematical Analysis (AREA)
  • Software Systems (AREA)
  • Computing Systems (AREA)
  • Complex Calculations (AREA)
  • Filters That Use Time-Delay Elements (AREA)
  • Cable Transmission Systems, Equalization Of Radio And Reduction Of Echo (AREA)
  • Calculators And Similar Devices (AREA)

Abstract

The present invention proposes a multiplier device performing multiplication of different powers of two serially in time (not in parallel) in order to further reduce the area needed for a hardware realization. By virtue thereof, it is enabled to use only one adder in connection with the multiplication which contributes to a reduced hardware amount and reduced required area for the hardware. A shifter means based on binary weighted shifting is used for shifting in connection with the multiplication, thereby reducing the required hardware amount (number of multiplexers and hardwired shifting elements) and thus reducing the area for hardware implementation still further. The present invention can be used in applications using digital multiplication, such as in digital signal processing DSP, digital filters and/or finite impulse response filters FIR filters as well as programmable and/or adaptive digital filters. As the multiplier is represented in CSD coding, the number of necessary shifting operations can be reduced and the number of necessary additions can be reduced, thus contributing to a reduced area needed for a hardware realization of a shifting means and a multiplier device on a silicon chip.
AU2001212724A 2000-10-16 2000-10-16 Multiplier and shift device using signed digit representation Abandoned AU2001212724A1 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/EP2000/010166 WO2002033537A1 (en) 2000-10-16 2000-10-16 Multiplier and shift device using signed digit representation

Publications (1)

Publication Number Publication Date
AU2001212724A1 true AU2001212724A1 (en) 2002-04-29

Family

ID=8164134

Family Applications (1)

Application Number Title Priority Date Filing Date
AU2001212724A Abandoned AU2001212724A1 (en) 2000-10-16 2000-10-16 Multiplier and shift device using signed digit representation

Country Status (7)

Country Link
US (1) US7257609B1 (en)
EP (1) EP1330700B1 (en)
CN (1) CN1306390C (en)
AT (1) ATE300761T1 (en)
AU (1) AU2001212724A1 (en)
DE (1) DE60021623T2 (en)
WO (1) WO2002033537A1 (en)

Families Citing this family (25)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8213467B2 (en) * 2004-04-08 2012-07-03 Sonosite, Inc. Systems and methods providing ASICs for use in multiple applications
WO2005114415A2 (en) * 2004-05-11 2005-12-01 North Dakota State University Parallel architecture for low power linear feedback shift registers
DE602004008904D1 (en) * 2004-07-13 2007-10-25 St Microelectronics Srl Device for digital signal processing using the CSD representation
US7680872B2 (en) * 2005-01-11 2010-03-16 Via Telecom Co., Ltd. Canonical signed digit (CSD) coefficient multiplier with optimization
WO2006103601A2 (en) * 2005-03-31 2006-10-05 Nxp B.V. Canonical signed digit multiplier
JP2007097089A (en) * 2005-09-30 2007-04-12 Yokogawa Electric Corp Coding circuit and coding device
US7680474B2 (en) * 2005-10-04 2010-03-16 Hypres Inc. Superconducting digital mixer
US7904841B1 (en) * 2007-10-12 2011-03-08 Lockheed Martin Corporation Method and system for optimizing digital filters
CN101840322B (en) * 2010-01-08 2016-03-09 北京中星微电子有限公司 The arithmetic system of the method that filter arithmetic element is multiplexing and wave filter
CN101866278B (en) * 2010-06-18 2013-05-15 广东工业大学 Asynchronous iteration 64-bit integer multiplier and computing method thereof
CN102314215B (en) * 2011-09-27 2014-03-12 西安电子科技大学 Low power consumption optimization method of decimal multiplier in integrated circuit system
EP2608015B1 (en) * 2011-12-21 2019-02-06 IMEC vzw System and method for implementing a multiplication
CN103051420B (en) * 2012-12-14 2015-04-08 无锡北邮感知技术产业研究院有限公司 Codebook generation method of MIMO (Multiple-Input Multiple-output) system
GB2535426B (en) * 2014-10-31 2021-08-11 Advanced Risc Mach Ltd Apparatus, method and program for calculating the result of a repeating iterative sum
US10313641B2 (en) 2015-12-04 2019-06-04 Google Llc Shift register with reduced wiring complexity
CN109194307B (en) * 2018-08-01 2022-05-27 南京中感微电子有限公司 Data processing method and system
US10761847B2 (en) * 2018-08-17 2020-09-01 Micron Technology, Inc. Linear feedback shift register for a reconfigurable logic unit
US10826529B2 (en) 2019-01-31 2020-11-03 Hong Kong Applied Science And Technology Research Institute Co., Ltd. Parallel LDPC decoder
WO2020155146A1 (en) * 2019-01-31 2020-08-06 Hong Kong Applied Science and Technology Research Institute Company Limited Parallel ldpc decoder
US10877729B2 (en) 2019-01-31 2020-12-29 Hong Kong Applied Science And Technology Research Institute Co., Ltd. Reconfigurable segmented scalable shifter
CN110515589B (en) * 2019-08-30 2024-04-09 上海寒武纪信息科技有限公司 Multiplier, data processing method, chip and electronic equipment
CN110515587B (en) * 2019-08-30 2024-01-19 上海寒武纪信息科技有限公司 Multiplier, data processing method, chip and electronic equipment
CN110413254B (en) * 2019-09-24 2020-01-10 上海寒武纪信息科技有限公司 Data processor, method, chip and electronic equipment
US11658643B2 (en) * 2021-01-18 2023-05-23 Raytheon Company Configurable multiplier-free multirate filter
US11575390B2 (en) 2021-07-02 2023-02-07 Hong Kong Applied Science and Technology Research Insitute Co., Ltd. Low-latency segmented quasi-cyclic low-density parity-check (QC-LDPC) decoder

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57141753A (en) * 1981-02-25 1982-09-02 Nec Corp Multiplication circuit
US4947364A (en) * 1985-10-23 1990-08-07 Hewlett-Packard Company Method in a computing system for performing a multiplication
US4967388A (en) 1988-04-21 1990-10-30 Harris Semiconductor Patents Inc. Truncated product partial canonical signed digit multiplier
US5253195A (en) 1991-09-26 1993-10-12 International Business Machines Corporation High speed multiplier
US5262974A (en) * 1991-10-28 1993-11-16 Trw Inc. Programmable canonic signed digit filter chip
JPH06259228A (en) * 1993-03-10 1994-09-16 Mitsubishi Electric Corp Multiplier
US5465222A (en) * 1994-02-14 1995-11-07 Tektronix, Inc. Barrel shifter or multiply/divide IC structure
US5978822A (en) 1995-12-29 1999-11-02 Atmel Corporation Circuit for rotating, left shifting, or right shifting bits
US6590931B1 (en) * 1999-12-09 2003-07-08 Koninklijke Philips Electronics N.V. Reconfigurable FIR filter using CSD coefficient representation
US7080115B2 (en) * 2002-05-22 2006-07-18 Broadcom Corporation Low-error canonic-signed-digit fixed-width multiplier, and method for designing same
US7277479B2 (en) * 2003-03-02 2007-10-02 Mediatek Inc. Reconfigurable fir filter

Also Published As

Publication number Publication date
DE60021623D1 (en) 2005-09-01
CN1306390C (en) 2007-03-21
EP1330700A1 (en) 2003-07-30
DE60021623T2 (en) 2006-06-01
EP1330700B1 (en) 2005-07-27
CN1454347A (en) 2003-11-05
WO2002033537A1 (en) 2002-04-25
US7257609B1 (en) 2007-08-14
ATE300761T1 (en) 2005-08-15

Similar Documents

Publication Publication Date Title
AU2001212724A1 (en) Multiplier and shift device using signed digit representation
EP0948133A2 (en) Digital filter with efficient quantization circuitry
KR940006211B1 (en) Finite impulse response filter
EP0693236B1 (en) Method and arrangement in a transposed digital fir filter for multiplying a binary input signal with tap coefficients and a method for designing a transposed digital filter
EP0975091A3 (en) Digital filter
US4750146A (en) Method and apparatus for compensating for the truncation error in a filtered signal by adding the error to the positive part of the signal and subtracting the error from the negative part of the signal
US20090150468A1 (en) Digital filter
TW200701138A (en) Interpolation process circuit
US7167514B2 (en) Processing of quinary data
US5912827A (en) Digital filter with low rolloff factor
Hong et al. Implementation of FIR filter on FPGA using DAOBC algorithm
WO1997009780A1 (en) Improved digital filter
Loganya et al. Low Power VLSI Architecture for Reconfigurable FIR Filter
Jimenez et al. Application of generalized sharpening technique for two-stage comb decimator filter design
KR20010062731A (en) Variable-gain digital filter
Ali Cascaded ripple carry adder based SRCSA for efficient FIR filter
JP3384756B2 (en) IIR digital low-pass filter
Zhu et al. ASIC implementation architecture for pulse shaping FIR filters in 3G mobile communications
Sendhilkumar et al. Design of high speed and low power new reconfigurable fir filter for DSP applications
US7080108B1 (en) Discrete filter having a tap selection circuit
KR100267251B1 (en) Method and system for minimizing Finite Impulse Response Filter
Tecpanecatl-Xihuitl et al. Efficient mutliplierless polyphase fir filter based on new distributed arithmetic architecture
JP2005094541A (en) Digital filter
TW202215780A (en) Filter circuits and associated signal processing methods
WO2003009473A1 (en) Processing of quinary data