ATE553435T1 - Programmierbare zugriffslatenzzeit in einem pseudo-multiportspeicher - Google Patents

Programmierbare zugriffslatenzzeit in einem pseudo-multiportspeicher

Info

Publication number
ATE553435T1
ATE553435T1 AT03725527T AT03725527T ATE553435T1 AT E553435 T1 ATE553435 T1 AT E553435T1 AT 03725527 T AT03725527 T AT 03725527T AT 03725527 T AT03725527 T AT 03725527T AT E553435 T1 ATE553435 T1 AT E553435T1
Authority
AT
Austria
Prior art keywords
facility
access latency
computer memory
input port
multiport memory
Prior art date
Application number
AT03725527T
Other languages
English (en)
Inventor
Jeroen Leijten
Original Assignee
Silicon Hive Bv
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Silicon Hive Bv filed Critical Silicon Hive Bv
Application granted granted Critical
Publication of ATE553435T1 publication Critical patent/ATE553435T1/de

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
    • G06F13/161—Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Multi Processors (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)
  • Executing Machine-Instructions (AREA)
  • Measurement And Recording Of Electrical Phenomena And Electrical Characteristics Of The Living Body (AREA)
AT03725527T 2002-05-24 2003-05-22 Programmierbare zugriffslatenzzeit in einem pseudo-multiportspeicher ATE553435T1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
EP02077041 2002-05-24
PCT/IB2003/002194 WO2003100618A2 (en) 2002-05-24 2003-05-22 Programmed access latency in mock multiport memory

Publications (1)

Publication Number Publication Date
ATE553435T1 true ATE553435T1 (de) 2012-04-15

Family

ID=29558362

Family Applications (1)

Application Number Title Priority Date Filing Date
AT03725527T ATE553435T1 (de) 2002-05-24 2003-05-22 Programmierbare zugriffslatenzzeit in einem pseudo-multiportspeicher

Country Status (7)

Country Link
US (1) US7231478B2 (de)
EP (1) EP1512078B1 (de)
JP (1) JP4566738B2 (de)
CN (1) CN100350401C (de)
AT (1) ATE553435T1 (de)
AU (1) AU2003228058A1 (de)
WO (1) WO2003100618A2 (de)

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US8005919B2 (en) 2002-11-18 2011-08-23 Aol Inc. Host-based intelligent results related to a character stream
US7640306B2 (en) 2002-11-18 2009-12-29 Aol Llc Reconfiguring an electronic message to effect an enhanced notification
CA2506585A1 (en) 2002-11-18 2004-06-03 Valerie Kucharewski People lists
US7590696B1 (en) 2002-11-18 2009-09-15 Aol Llc Enhanced buddy list using mobile device identifiers
US8122137B2 (en) 2002-11-18 2012-02-21 Aol Inc. Dynamic location of a subordinate user
US7899862B2 (en) 2002-11-18 2011-03-01 Aol Inc. Dynamic identification of other users to an online user
US7428580B2 (en) 2003-11-26 2008-09-23 Aol Llc Electronic message forwarding
US8701014B1 (en) 2002-11-18 2014-04-15 Facebook, Inc. Account linking
US7613776B1 (en) 2003-03-26 2009-11-03 Aol Llc Identifying and using identities deemed to be known to a user
US7653693B2 (en) 2003-09-05 2010-01-26 Aol Llc Method and system for capturing instant messages
EP1896983B1 (de) * 2005-06-30 2011-08-10 Imec Speicheranordnung für mehrprozessorsysteme
US8560795B2 (en) 2005-06-30 2013-10-15 Imec Memory arrangement for multi-processor systems including a memory queue
EP1955175A1 (de) * 2005-09-09 2008-08-13 Freescale Semiconductor, Inc. Verbindungseinrichtung und verfahren zum entwurf einer verbindungseinrichtung
EP2132630A1 (de) * 2007-03-28 2009-12-16 Nxp B.V. Mehrfachverarbeitungssystem und verfahren
CN102799549A (zh) * 2011-05-23 2012-11-28 中兴通讯股份有限公司 一种多源端口的数据处理方法及装置
KR101862799B1 (ko) 2011-12-12 2018-05-31 삼성전자주식회사 메모리 컨트롤러 및 메모리 컨트롤 방법
US9146747B2 (en) * 2013-08-08 2015-09-29 Linear Algebra Technologies Limited Apparatus, systems, and methods for providing configurable computational imaging pipeline
US9940264B2 (en) * 2014-10-10 2018-04-10 International Business Machines Corporation Load and store ordering for a strongly ordered simultaneous multithreading core
CN105701040B (zh) * 2014-11-28 2018-12-07 杭州华为数字技术有限公司 一种激活内存的方法及装置
US11216212B2 (en) * 2019-03-19 2022-01-04 International Business Machines Corporation Minimizing conflicts in multiport banked memory arrays
CN112231254B (zh) * 2020-09-22 2022-04-26 深圳云天励飞技术股份有限公司 存储器仲裁方法及存储器控制器

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Also Published As

Publication number Publication date
CN1656461A (zh) 2005-08-17
EP1512078A2 (de) 2005-03-09
AU2003228058A1 (en) 2003-12-12
WO2003100618A2 (en) 2003-12-04
AU2003228058A8 (en) 2003-12-12
JP4566738B2 (ja) 2010-10-20
US20050177689A1 (en) 2005-08-11
WO2003100618A3 (en) 2004-09-10
CN100350401C (zh) 2007-11-21
US7231478B2 (en) 2007-06-12
EP1512078B1 (de) 2012-04-11
JP2005527040A (ja) 2005-09-08

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