ATE552610T1 - Verfahren und vorrichtung zur prüfung eines chips vor dem bonden - Google Patents

Verfahren und vorrichtung zur prüfung eines chips vor dem bonden

Info

Publication number
ATE552610T1
ATE552610T1 AT09167663T AT09167663T ATE552610T1 AT E552610 T1 ATE552610 T1 AT E552610T1 AT 09167663 T AT09167663 T AT 09167663T AT 09167663 T AT09167663 T AT 09167663T AT E552610 T1 ATE552610 T1 AT E552610T1
Authority
AT
Austria
Prior art keywords
chip
testing
bonding
handling
connection
Prior art date
Application number
AT09167663T
Other languages
English (en)
Inventor
Johannes Schuster
Original Assignee
Kulicke & Soffa Die Bonding Gmbh
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kulicke & Soffa Die Bonding Gmbh filed Critical Kulicke & Soffa Die Bonding Gmbh
Application granted granted Critical
Publication of ATE552610T1 publication Critical patent/ATE552610T1/de

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67011—Apparatus for manufacture or treatment
    • H01L21/67132—Apparatus for placing on an insulating substrate, e.g. tape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67011—Apparatus for manufacture or treatment
    • H01L21/67144—Apparatus for mounting on conductive members, e.g. leadframes or conductors on insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6838—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping with gripping and holding devices using a vacuum; Bernoulli devices

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)
  • Die Bonding (AREA)
  • Wire Bonding (AREA)
AT09167663T 2009-08-11 2009-08-11 Verfahren und vorrichtung zur prüfung eines chips vor dem bonden ATE552610T1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
EP09167663A EP2284863B1 (de) 2009-08-11 2009-08-11 Verfahren und Vorrichtung zur Prüfung eines Chips vor dem Bonden

Publications (1)

Publication Number Publication Date
ATE552610T1 true ATE552610T1 (de) 2012-04-15

Family

ID=41138126

Family Applications (1)

Application Number Title Priority Date Filing Date
AT09167663T ATE552610T1 (de) 2009-08-11 2009-08-11 Verfahren und vorrichtung zur prüfung eines chips vor dem bonden

Country Status (6)

Country Link
EP (1) EP2284863B1 (de)
KR (2) KR101953146B1 (de)
CN (2) CN102549712B (de)
AT (1) ATE552610T1 (de)
SG (1) SG178101A1 (de)
WO (1) WO2011018375A1 (de)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107658248B (zh) * 2011-06-03 2021-06-22 豪锐恩科技私人有限公司 用于将半导体芯片置于衬底上的系统
CH705370A1 (de) * 2011-07-31 2013-01-31 Kulicke & Soffa Die Bonding Gmbh Verfahren und Vorrichtung zur Inspektion eines Halbleiterchips vor der Montage.
US9093549B2 (en) 2013-07-02 2015-07-28 Kulicke And Soffa Industries, Inc. Bond heads for thermocompression bonders, thermocompression bonders, and methods of operating the same
KR102122038B1 (ko) * 2018-05-28 2020-06-11 세메스 주식회사 본딩 툴과 이를 포함하는 다이 본딩 장치 및 이를 이용하는 다이 본딩 방법
CN109712912B (zh) * 2018-12-06 2023-07-18 通富微电子股份有限公司 一种芯片倒装设备及方法

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5080549A (en) 1987-05-11 1992-01-14 Epsilon Technology, Inc. Wafer handling system with Bernoulli pick-up
JPH0755711A (ja) * 1993-08-12 1995-03-03 Sumitomo Electric Ind Ltd 半導体デバイスの検査装置
JPH07285087A (ja) * 1994-04-15 1995-10-31 Rohm Co Ltd 半導体チップのピックアップ検査装置
JP2000260789A (ja) * 1999-03-10 2000-09-22 Nec Kansai Ltd ダイボンダ
EP1189496B1 (de) * 2000-09-13 2009-10-28 Esec AG Vorrichtung für die Montage von Halbleiterchips
WO2005013354A1 (ja) * 2003-07-30 2005-02-10 Nec Machinery Corporation ワーク移載手段、画像認識装置および位置決め方法
CH697213A5 (de) 2004-05-19 2008-06-25 Alphasem Ag Verfahren und Vorrichtung zum Ablösen eines auf eine flexible Folie geklebten Bauteils.
JP2006108281A (ja) * 2004-10-04 2006-04-20 Matsushita Electric Ind Co Ltd 電子部品ピックアップ方法および電子部品搭載方法ならびに電子部品搭載装置
US8914971B2 (en) 2006-04-12 2014-12-23 Kulicke & Soffa Die Bonding Gmbh Method and apparatus for the placement of electronic components, in particular semi conductor chips on a substrate

Also Published As

Publication number Publication date
EP2284863A1 (de) 2011-02-16
KR101953146B1 (ko) 2019-02-28
CN105047588A (zh) 2015-11-11
SG178101A1 (en) 2012-03-29
KR20120059524A (ko) 2012-06-08
CN102549712B (zh) 2015-07-29
KR20180037063A (ko) 2018-04-10
EP2284863B1 (de) 2012-04-04
CN102549712A (zh) 2012-07-04
WO2011018375A1 (en) 2011-02-17
CN105047588B (zh) 2019-06-21

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