ATE543206T1 - Oberflächenbearbeitung nach selektivem ätzen - Google Patents

Oberflächenbearbeitung nach selektivem ätzen

Info

Publication number
ATE543206T1
ATE543206T1 AT06794439T AT06794439T ATE543206T1 AT E543206 T1 ATE543206 T1 AT E543206T1 AT 06794439 T AT06794439 T AT 06794439T AT 06794439 T AT06794439 T AT 06794439T AT E543206 T1 ATE543206 T1 AT E543206T1
Authority
AT
Austria
Prior art keywords
layer
selective etching
sige
surface processing
strained silicon
Prior art date
Application number
AT06794439T
Other languages
English (en)
Inventor
Cecile Delattre
Original Assignee
Soitec Silicon On Insulator
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Soitec Silicon On Insulator filed Critical Soitec Silicon On Insulator
Application granted granted Critical
Publication of ATE543206T1 publication Critical patent/ATE543206T1/de

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02041—Cleaning
    • H01L21/02043—Cleaning before device manufacture, i.e. Begin-Of-Line process
    • H01L21/02052—Wet cleaning only
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/974—Substrate surface preparation

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Weting (AREA)
  • Cleaning Or Drying Semiconductors (AREA)
  • Crystals, And After-Treatments Of Crystals (AREA)
  • Manufacture Or Reproduction Of Printing Formes (AREA)
  • Shaping Of Tube Ends By Bending Or Straightening (AREA)
AT06794439T 2005-05-19 2006-05-18 Oberflächenbearbeitung nach selektivem ätzen ATE543206T1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR0505014A FR2886052B1 (fr) 2005-05-19 2005-05-19 Traitement de surface apres gravure selective
PCT/FR2006/050455 WO2007000537A2 (fr) 2005-05-19 2006-05-18 Traitement de surface apres gravure selective.

Publications (1)

Publication Number Publication Date
ATE543206T1 true ATE543206T1 (de) 2012-02-15

Family

ID=35610234

Family Applications (1)

Application Number Title Priority Date Filing Date
AT06794439T ATE543206T1 (de) 2005-05-19 2006-05-18 Oberflächenbearbeitung nach selektivem ätzen

Country Status (7)

Country Link
US (1) US7439189B2 (de)
EP (1) EP1883953B1 (de)
JP (1) JP2008541467A (de)
AT (1) ATE543206T1 (de)
FR (1) FR2886052B1 (de)
TW (1) TW200701360A (de)
WO (1) WO2007000537A2 (de)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4306724B2 (ja) * 2006-12-19 2009-08-05 セイコーエプソン株式会社 半導体装置の製造方法
US8461055B2 (en) * 2007-05-03 2013-06-11 Soitec Process for preparing cleaned surfaces of strained silicon
CN103311172A (zh) * 2012-03-16 2013-09-18 中芯国际集成电路制造(上海)有限公司 Soi衬底的形成方法
CN105655248B (zh) * 2016-03-22 2018-06-05 河南芯睿电子科技有限公司 一种非抛光单晶硅基器件光刻对准标记的碱腐蚀加工方法

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5464480A (en) * 1993-07-16 1995-11-07 Legacy Systems, Inc. Process and apparatus for the treatment of semiconductor wafers in a fluid
JP2914555B2 (ja) * 1994-08-30 1999-07-05 信越半導体株式会社 半導体シリコンウェーハの洗浄方法
US6180496B1 (en) 1997-08-29 2001-01-30 Silicon Genesis Corporation In situ plasma wafer bonding method
JP3662484B2 (ja) * 2000-08-09 2005-06-22 エム・エフエスアイ株式会社 ウェット処理方法及びウェット処理装置
US7183177B2 (en) 2000-08-11 2007-02-27 Applied Materials, Inc. Silicon-on-insulator wafer transfer method using surface activation plasma immersion ion implantation for wafer-to-wafer adhesion enhancement
US6780759B2 (en) 2001-05-09 2004-08-24 Silicon Genesis Corporation Method for multi-frequency bonding
JP2003173999A (ja) * 2001-12-07 2003-06-20 Mitsubishi Electric Corp 半導体基板洗浄装置、半導体基板洗浄方法および半導体装置の製造方法
FR2842349B1 (fr) 2002-07-09 2005-02-18 Transfert d'une couche mince a partir d'une plaquette comprenant une couche tampon
US6953736B2 (en) 2002-07-09 2005-10-11 S.O.I.Tec Silicon On Insulator Technologies S.A. Process for transferring a layer of strained semiconductor material
JP4182818B2 (ja) * 2003-06-20 2008-11-19 株式会社Ｓｕｍｃｏ 半導体基板の製造方法

Also Published As

Publication number Publication date
FR2886052B1 (fr) 2007-11-23
WO2007000537A3 (fr) 2007-04-12
WO2007000537A2 (fr) 2007-01-04
JP2008541467A (ja) 2008-11-20
US20060264008A1 (en) 2006-11-23
US7439189B2 (en) 2008-10-21
TW200701360A (en) 2007-01-01
FR2886052A1 (fr) 2006-11-24
EP1883953A2 (de) 2008-02-06
EP1883953B1 (de) 2012-01-25

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