ATE540494T1 - Verfahren und vorrichtung zur ausrichtung von daten in einer breiten quellensynchronen parallelen hochgeschwindigkeitsverbindung - Google Patents

Verfahren und vorrichtung zur ausrichtung von daten in einer breiten quellensynchronen parallelen hochgeschwindigkeitsverbindung

Info

Publication number
ATE540494T1
ATE540494T1 AT05851478T AT05851478T ATE540494T1 AT E540494 T1 ATE540494 T1 AT E540494T1 AT 05851478 T AT05851478 T AT 05851478T AT 05851478 T AT05851478 T AT 05851478T AT E540494 T1 ATE540494 T1 AT E540494T1
Authority
AT
Austria
Prior art keywords
clock
group
alignment
data
high speed
Prior art date
Application number
AT05851478T
Other languages
English (en)
Inventor
Dipankar Bhattacharya
Bangalore Priyadarshan
Jaushin Lee
Boulch Francois Gautier-Le
Original Assignee
Cisco Tech Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Cisco Tech Inc filed Critical Cisco Tech Inc
Application granted granted Critical
Publication of ATE540494T1 publication Critical patent/ATE540494T1/de

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
    • G06F13/4291—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus using a clocked protocol
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/06—Synchronising arrangements
    • H04J3/062—Synchronisation of signals having the same nominal but fluctuating bit rates, e.g. using buffers
    • H04J3/0632—Synchronisation of packets and cells, e.g. transmission of voice via a packet network, circuit emulation service [CES]
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/14—Channel dividing arrangements, i.e. in which a single bit stream is divided between several baseband channels and reassembled at the receiver
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/0008—Synchronisation information channels, e.g. clock distribution lines
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/04—Speed or phase control by synchronisation signals
    • H04L7/041—Speed or phase control by synchronisation signals using special codes as synchronising signal

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Multimedia (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Information Transfer Systems (AREA)
  • Communication Control (AREA)
  • Time-Division Multiplex Systems (AREA)
AT05851478T 2004-11-15 2005-11-09 Verfahren und vorrichtung zur ausrichtung von daten in einer breiten quellensynchronen parallelen hochgeschwindigkeitsverbindung ATE540494T1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/989,703 US7720107B2 (en) 2003-06-16 2004-11-15 Aligning data in a wide, high-speed, source synchronous parallel link
PCT/US2005/040629 WO2006055374A2 (en) 2004-11-15 2005-11-09 Method and apparatus for aligning data in a wide, high-speed, source synchronous parallel link

Publications (1)

Publication Number Publication Date
ATE540494T1 true ATE540494T1 (de) 2012-01-15

Family

ID=36407632

Family Applications (1)

Application Number Title Priority Date Filing Date
AT05851478T ATE540494T1 (de) 2004-11-15 2005-11-09 Verfahren und vorrichtung zur ausrichtung von daten in einer breiten quellensynchronen parallelen hochgeschwindigkeitsverbindung

Country Status (4)

Country Link
US (1) US7720107B2 (de)
EP (1) EP1813039B1 (de)
AT (1) ATE540494T1 (de)
WO (1) WO2006055374A2 (de)

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TWI306343B (en) * 2005-09-01 2009-02-11 Via Tech Inc Bus receiver and method of deskewing bus signals
US7415569B2 (en) * 2006-03-22 2008-08-19 Infineon Technologies Ag Memory including a write training block
US7454559B2 (en) * 2006-03-22 2008-11-18 Infineon Technologies Ag Filtering bit position in a memory
US7860202B2 (en) * 2006-04-13 2010-12-28 Etron Technology, Inc. Method and circuit for transferring data stream across multiple clock domains
KR100915387B1 (ko) 2006-06-22 2009-09-03 삼성전자주식회사 병렬 인터페이스의 데이터 신호와 클럭 신호 간의 스큐를보상하는 방법 및 장치
US7555668B2 (en) * 2006-07-18 2009-06-30 Integrated Device Technology, Inc. DRAM interface circuits that support fast deskew calibration and methods of operating same
US7835479B2 (en) * 2006-10-16 2010-11-16 Advantest Corporation Jitter injection apparatus, jitter injection method, testing apparatus, and communication chip
US8185854B1 (en) * 2006-11-22 2012-05-22 Altera Corporation Method and apparatus for performing parallel slack computation within a shared netlist region
US7926011B1 (en) * 2007-01-10 2011-04-12 Cadence Design Systems, Inc. System and method of generating hierarchical block-level timing constraints from chip-level timing constraints
US8640066B1 (en) * 2007-01-10 2014-01-28 Cadence Design Systems, Inc. Multi-phase models for timing closure of integrated circuit designs
US8977995B1 (en) * 2007-01-10 2015-03-10 Cadence Design Systems, Inc. Timing budgeting of nested partitions for hierarchical integrated circuit designs
US8365113B1 (en) * 2007-01-10 2013-01-29 Cadence Design Systems, Inc. Flow methodology for single pass parallel hierarchical timing closure of integrated circuit designs
JP5056110B2 (ja) * 2007-03-28 2012-10-24 ソニー株式会社 集積回路生成装置およびその方法
EP2220566A2 (de) * 2007-12-05 2010-08-25 Nxp B.V. Quellensynchrone datenverbindung für system-on-chip-gestaltung
US8611178B2 (en) * 2011-11-11 2013-12-17 Qualcomm Incorporated Device and method to perform memory operations at a clock domain crossing
KR102140057B1 (ko) * 2014-01-20 2020-07-31 삼성전자 주식회사 디스큐 기능을 갖는 고속 데이터 인터페이스 방법 및 그 장치
US9832006B1 (en) * 2016-05-24 2017-11-28 Intel Corporation Method, apparatus and system for deskewing parallel interface links
US10129166B2 (en) 2016-06-21 2018-11-13 Intel Corporation Low latency re-timer
US10983944B2 (en) 2019-01-17 2021-04-20 Oracle International Corporation Method for training multichannel data receiver timing

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JPH04176232A (ja) * 1990-11-09 1992-06-23 Hitachi Ltd パケット通信方式およびパケット通信装置
JP2694807B2 (ja) * 1993-12-16 1997-12-24 日本電気株式会社 データ伝送方式
US5734685A (en) * 1996-01-03 1998-03-31 Credence Systems Corporation Clock signal deskewing system
US6536025B2 (en) * 2001-05-14 2003-03-18 Intel Corporation Receiver deskewing of multiple source synchronous bits from a parallel bus
US6839862B2 (en) * 2001-05-31 2005-01-04 Koninklijke Philips Electronics N.V. Parallel data communication having skew intolerant data groups
US6920576B2 (en) * 2001-05-31 2005-07-19 Koninklijke Philips Electronics N.V. Parallel data communication having multiple sync codes
US7085950B2 (en) 2001-09-28 2006-08-01 Koninklijke Philips Electronics N.V. Parallel data communication realignment of data sent in multiple groups
US6665218B2 (en) 2001-12-05 2003-12-16 Agilent Technologies, Inc. Self calibrating register for source synchronous clocking systems
US20030112827A1 (en) * 2001-12-13 2003-06-19 International Business Machines Corporation Method and apparatus for deskewing parallel serial data channels using asynchronous elastic buffers
US6996738B2 (en) * 2002-04-15 2006-02-07 Broadcom Corporation Robust and scalable de-skew method for data path skew control
KR100440585B1 (ko) * 2002-05-24 2004-07-19 한국전자통신연구원 대용량 데이터의 분할 전송을 위한 다중 레인간의 비틀림정렬 장치 및 방법, 그리고 기록매체
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Also Published As

Publication number Publication date
EP1813039A2 (de) 2007-08-01
US20050066142A1 (en) 2005-03-24
WO2006055374A2 (en) 2006-05-26
WO2006055374A3 (en) 2007-01-18
EP1813039B1 (de) 2012-01-04
US7720107B2 (en) 2010-05-18
EP1813039A4 (de) 2010-06-02

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