ATE539490T1 - Viterbi dekoder mit zwei speichern angepasst für gnss signale - Google Patents

Viterbi dekoder mit zwei speichern angepasst für gnss signale

Info

Publication number
ATE539490T1
ATE539490T1 AT10164997T AT10164997T ATE539490T1 AT E539490 T1 ATE539490 T1 AT E539490T1 AT 10164997 T AT10164997 T AT 10164997T AT 10164997 T AT10164997 T AT 10164997T AT E539490 T1 ATE539490 T1 AT E539490T1
Authority
AT
Austria
Prior art keywords
memory
viterbi decoder
gnss signals
memory adapted
fields
Prior art date
Application number
AT10164997T
Other languages
English (en)
Inventor
Pierre-Yves Dumas
Yves Clauzel
Jean-Michel Perre
Original Assignee
Thales Sa
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Thales Sa filed Critical Thales Sa
Application granted granted Critical
Publication of ATE539490T1 publication Critical patent/ATE539490T1/de

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/37—Decoding methods or techniques, not specific to the particular type of coding provided for in groups H03M13/03 - H03M13/35
    • H03M13/39—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes
    • H03M13/41—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes using the Viterbi algorithm or Viterbi processors
    • H03M13/4161—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes using the Viterbi algorithm or Viterbi processors implementing path management
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/37—Decoding methods or techniques, not specific to the particular type of coding provided for in groups H03M13/03 - H03M13/35
    • H03M13/39—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes
    • H03M13/41—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes using the Viterbi algorithm or Viterbi processors
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/65—Purpose and implementation aspects
    • H03M13/6508—Flexibility, adaptability, parametrability and configurability of the implementation
    • H03M13/6516—Support of multiple code parameters, e.g. generalized Reed-Solomon decoder for a variety of generator polynomials or Galois fields
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/65—Purpose and implementation aspects
    • H03M13/6569—Implementation on processors, e.g. DSPs, or software implementations

Landscapes

  • Physics & Mathematics (AREA)
  • Probability & Statistics with Applications (AREA)
  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Error Detection And Correction (AREA)
AT10164997T 2009-06-09 2010-06-04 Viterbi dekoder mit zwei speichern angepasst für gnss signale ATE539490T1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR0902782A FR2946480B1 (fr) 2009-06-09 2009-06-09 Recepteur equipe d'un decodeur de viterbi a treillis

Publications (1)

Publication Number Publication Date
ATE539490T1 true ATE539490T1 (de) 2012-01-15

Family

ID=41480110

Family Applications (1)

Application Number Title Priority Date Filing Date
AT10164997T ATE539490T1 (de) 2009-06-09 2010-06-04 Viterbi dekoder mit zwei speichern angepasst für gnss signale

Country Status (5)

Country Link
US (1) US8365056B2 (de)
EP (1) EP2262116B1 (de)
AT (1) ATE539490T1 (de)
CA (1) CA2707198A1 (de)
FR (1) FR2946480B1 (de)

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2686991A1 (fr) 1992-02-05 1993-07-30 Sextant Avionique Procede, systeme et processeur de communication entre une pluralite de sous-ensembles d'un equipement.
DE59509663D1 (de) * 1995-10-21 2001-11-08 Micronas Gmbh Logischer Block für einen Viterbi-Decoder
US6477680B2 (en) * 1998-06-26 2002-11-05 Agere Systems Inc. Area-efficient convolutional decoder
US6597743B1 (en) * 1999-12-07 2003-07-22 Ericsson Inc. Reduced search symbol estimation algorithm
WO2001073999A1 (en) * 2000-03-24 2001-10-04 Atheros Communications, Inc. Decoding system and method for digital communications
DE20109857U1 (de) * 2000-07-03 2001-10-31 Infineon Technologies AG, 81669 München Viterbi-Entzerrer
DE102004038754A1 (de) * 2004-08-09 2006-02-23 Micronas Gmbh Decoder und Verfahren zum Durchführen eines Viterbi-Algorithmus
GB2422074B (en) * 2005-01-10 2007-06-06 Toshiba Res Europ Ltd Signal decoding methods and apparatus
US7603613B2 (en) * 2005-02-17 2009-10-13 Samsung Electronics Co., Ltd. Viterbi decoder architecture for use in software-defined radio systems
FR2898998B1 (fr) 2006-03-21 2008-07-25 Thales Sa Procede et dispositif de calcul de correlation rapide
US8111767B2 (en) * 2007-05-31 2012-02-07 Renesas Electronics Corporation Adaptive sliding block Viterbi decoder

Also Published As

Publication number Publication date
FR2946480B1 (fr) 2011-06-17
FR2946480A1 (fr) 2010-12-10
US8365056B2 (en) 2013-01-29
US20100313103A1 (en) 2010-12-09
EP2262116A1 (de) 2010-12-15
CA2707198A1 (en) 2010-12-09
EP2262116B1 (de) 2011-12-28

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