ATE524896T1 - Verfahren und vorrichtung zum prüfen eines sende- und empfangssystems - Google Patents

Verfahren und vorrichtung zum prüfen eines sende- und empfangssystems

Info

Publication number
ATE524896T1
ATE524896T1 AT06780059T AT06780059T ATE524896T1 AT E524896 T1 ATE524896 T1 AT E524896T1 AT 06780059 T AT06780059 T AT 06780059T AT 06780059 T AT06780059 T AT 06780059T AT E524896 T1 ATE524896 T1 AT E524896T1
Authority
AT
Austria
Prior art keywords
duty cycle
testing
receiver
transmitting
jitter
Prior art date
Application number
AT06780059T
Other languages
English (en)
Inventor
Rodger F Schuttert
Geertjan Joordens
Willem F Slendebroek
Original Assignee
Nxp Bv
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nxp Bv filed Critical Nxp Bv
Application granted granted Critical
Publication of ATE524896T1 publication Critical patent/ATE524896T1/de

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/20—Arrangements for detecting or preventing errors in the information received using signal quality detector
    • H04L1/205—Arrangements for detecting or preventing errors in the information received using signal quality detector jitter monitoring
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/31725—Timing aspects, e.g. clock distribution, skew, propagation delay
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/319—Tester hardware, i.e. output processing circuits
    • G01R31/3193—Tester hardware, i.e. output processing circuits with comparison between actual response and known fault free response
    • G01R31/31937—Timing aspects, e.g. measuring propagation delay
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/24—Testing correct operation
    • H04L1/242—Testing correct operation by comparing a transmitted test signal with a locally generated replica

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Quality & Reliability (AREA)
  • Dc Digital Transmission (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)
AT06780059T 2005-07-15 2006-07-12 Verfahren und vorrichtung zum prüfen eines sende- und empfangssystems ATE524896T1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
EP05106522 2005-07-15
PCT/IB2006/052372 WO2007010452A2 (en) 2005-07-15 2006-07-12 Emulation and debug interfaces for testing an integrated circuit with an asynchronous microcontroller

Publications (1)

Publication Number Publication Date
ATE524896T1 true ATE524896T1 (de) 2011-09-15

Family

ID=37507336

Family Applications (1)

Application Number Title Priority Date Filing Date
AT06780059T ATE524896T1 (de) 2005-07-15 2006-07-12 Verfahren und vorrichtung zum prüfen eines sende- und empfangssystems

Country Status (7)

Country Link
US (1) US9838165B2 (de)
EP (1) EP1908205B1 (de)
JP (1) JP2009501480A (de)
CN (1) CN101223726B (de)
AT (1) ATE524896T1 (de)
TW (1) TW200719617A (de)
WO (1) WO2007010452A2 (de)

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008141668A (ja) * 2006-12-05 2008-06-19 Sumitomo Electric Ind Ltd 光受信装置
WO2010018544A1 (en) * 2008-08-12 2010-02-18 Nxp B.V. Testing of a transmission and reception system
KR101659313B1 (ko) * 2011-03-17 2016-09-26 한화테크윈 주식회사 신호 송수신 시스템 및 신호 송수신 방법
US8994277B2 (en) * 2011-08-30 2015-03-31 Novatek Microelectronics Corp. LED device, LED driving circuit and method
DE102012006228B3 (de) * 2012-03-24 2013-06-20 Eads Deutschland Gmbh Verfahren zum Selbsttest eines reaktiven Funkstörers
US9088399B1 (en) * 2014-02-03 2015-07-21 Xilinx, Inc. Circuit and method for testing jitter tolerance
CN104954044A (zh) * 2014-03-28 2015-09-30 北京大学 一种基于bist的高速串行io接口抖动容限测试方法和电路
KR101684801B1 (ko) * 2015-10-08 2016-12-09 한국과학기술원 최적의 비트 에러율과 실시간 적응 등화를 위한 시그마 추적 아이다이어그램 모니터 방법 및 장치
TWI637185B (zh) * 2017-01-03 2018-10-01 奇景光電股份有限公司 時脈抖動的內建自我測試電路
EP3923005B1 (de) 2020-06-11 2024-08-07 NXP USA, Inc. Selbsttest von einem arbeitszyklusdetektor
KR20220170244A (ko) 2021-06-22 2022-12-29 삼성전자주식회사 클록 변환 장치, 이를 포함하는 테스트 시스템 및 테스트 시스템의 동작방법
US11662381B2 (en) 2021-08-18 2023-05-30 International Business Machines Corporation Self-contained built-in self-test circuit with phase-shifting abilities for high-speed receivers
US11528102B1 (en) 2021-08-18 2022-12-13 International Business Machines Corporation Built-in-self-test and characterization of a high speed serial link receiver

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5889435A (en) 1997-06-30 1999-03-30 Sun Microsystems, Inc. On-chip PLL phase and jitter self-test circuit
US6298458B1 (en) * 1999-01-04 2001-10-02 International Business Machines Corporation System and method for manufacturing test of a physical layer transceiver
US6873939B1 (en) * 2001-02-02 2005-03-29 Rambus Inc. Method and apparatus for evaluating and calibrating a signaling system
US6772382B2 (en) * 2001-05-02 2004-08-03 Teradyne, Inc. Driver for integrated circuit chip tester
US7120215B2 (en) * 2001-12-12 2006-10-10 Via Technologies, Inc. Apparatus and method for on-chip jitter measurement
US7313178B2 (en) * 2002-04-10 2007-12-25 International Business Machines Corporation Transceiver for receiving and transmitting data over a network and method for testing the same
TWI236220B (en) * 2003-09-30 2005-07-11 Ali Corp Automatic correction device and method of clock duty cycle
US20060182187A1 (en) * 2005-02-11 2006-08-17 Likovich Robert B Jr Automatic reconfiguration of an I/O bus to correct for an error bit
US7612592B2 (en) * 2005-12-22 2009-11-03 Agere Systems, Inc. Programmable duty-cycle generator

Also Published As

Publication number Publication date
WO2007010452A3 (en) 2007-04-05
CN101223726A (zh) 2008-07-16
US9838165B2 (en) 2017-12-05
JP2009501480A (ja) 2009-01-15
EP1908205B1 (de) 2011-09-14
CN101223726B (zh) 2011-10-05
TW200719617A (en) 2007-05-16
WO2007010452A2 (en) 2007-01-25
EP1908205A2 (de) 2008-04-09
US20090105978A1 (en) 2009-04-23

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