ATE520150T1 - Verfahren zur trennung von chips - Google Patents

Verfahren zur trennung von chips

Info

Publication number
ATE520150T1
ATE520150T1 AT05447213T AT05447213T ATE520150T1 AT E520150 T1 ATE520150 T1 AT E520150T1 AT 05447213 T AT05447213 T AT 05447213T AT 05447213 T AT05447213 T AT 05447213T AT E520150 T1 ATE520150 T1 AT E520150T1
Authority
AT
Austria
Prior art keywords
stack
feol
substrate layer
trenches
singulating
Prior art date
Application number
AT05447213T
Other languages
English (en)
Inventor
Eric Beyne
Bart Swinnen
Serge Vanhaelemeersch
Original Assignee
Imec
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Imec filed Critical Imec
Application granted granted Critical
Publication of ATE520150T1 publication Critical patent/ATE520150T1/de

Links

Classifications

    • H10P54/00—

Landscapes

  • Dicing (AREA)
AT05447213T 2004-09-24 2005-09-21 Verfahren zur trennung von chips ATE520150T1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US61291504P 2004-09-24 2004-09-24
EP04447271A EP1670055A1 (de) 2004-12-09 2004-12-09 Verfahren zur Trennung von Chips

Publications (1)

Publication Number Publication Date
ATE520150T1 true ATE520150T1 (de) 2011-08-15

Family

ID=34933126

Family Applications (1)

Application Number Title Priority Date Filing Date
AT05447213T ATE520150T1 (de) 2004-09-24 2005-09-21 Verfahren zur trennung von chips

Country Status (2)

Country Link
EP (1) EP1670055A1 (de)
AT (1) ATE520150T1 (de)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101620980B (zh) * 2008-06-30 2012-01-25 中芯国际集成电路制造(上海)有限公司 后段制程模拟基底及其形成方法
US11769768B2 (en) 2020-06-01 2023-09-26 Wolfspeed, Inc. Methods for pillar connection on frontside and passive device integration on backside of die

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE1514928A1 (de) * 1966-02-18 1969-08-14 Telefunken Patent Verfahren zur Herstellung von mehreren Halbleiterbauelementen
JPH0215652A (ja) * 1988-07-01 1990-01-19 Mitsubishi Electric Corp 半導体装置及びその製造方法
DE4317721C1 (de) * 1993-05-27 1994-07-21 Siemens Ag Verfahren zur Vereinzelung von Chips aus einem Wafer
US5691248A (en) * 1995-07-26 1997-11-25 International Business Machines Corporation Methods for precise definition of integrated circuit chip edges

Also Published As

Publication number Publication date
EP1670055A1 (de) 2006-06-14

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Legal Events

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