ATE470189T1 - Speicherbefehls-handler zur verwendung in einem bildsignalprozessor mit einer datengestützten architektur - Google Patents

Speicherbefehls-handler zur verwendung in einem bildsignalprozessor mit einer datengestützten architektur

Info

Publication number
ATE470189T1
ATE470189T1 AT04754790T AT04754790T ATE470189T1 AT E470189 T1 ATE470189 T1 AT E470189T1 AT 04754790 T AT04754790 T AT 04754790T AT 04754790 T AT04754790 T AT 04754790T AT E470189 T1 ATE470189 T1 AT E470189T1
Authority
AT
Austria
Prior art keywords
signal processor
image signal
data
memory
command handler
Prior art date
Application number
AT04754790T
Other languages
English (en)
Inventor
Louis Lippincott
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Application granted granted Critical
Publication of ATE470189T1 publication Critical patent/ATE470189T1/de

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T1/00—General purpose image data processing
    • G06T1/60—Memory management
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T1/00—General purpose image data processing
    • G06T1/20—Processor architectures; Processor configuration, e.g. pipelining

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Engineering & Computer Science (AREA)
  • Image Processing (AREA)
  • Image Input (AREA)
AT04754790T 2003-06-27 2004-06-09 Speicherbefehls-handler zur verwendung in einem bildsignalprozessor mit einer datengestützten architektur ATE470189T1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/609,042 US7088371B2 (en) 2003-06-27 2003-06-27 Memory command handler for use in an image signal processor having a data driven architecture
PCT/US2004/018291 WO2005006207A2 (en) 2003-06-27 2004-06-09 Memory command handler for use in an image signal processor having a data driven architecture

Publications (1)

Publication Number Publication Date
ATE470189T1 true ATE470189T1 (de) 2010-06-15

Family

ID=33540745

Family Applications (1)

Application Number Title Priority Date Filing Date
AT04754790T ATE470189T1 (de) 2003-06-27 2004-06-09 Speicherbefehls-handler zur verwendung in einem bildsignalprozessor mit einer datengestützten architektur

Country Status (9)

Country Link
US (1) US7088371B2 (de)
EP (1) EP1639495B1 (de)
JP (1) JP4344383B2 (de)
KR (1) KR100818819B1 (de)
AT (1) ATE470189T1 (de)
DE (1) DE602004027493D1 (de)
MY (1) MY137269A (de)
TW (1) TWI269168B (de)
WO (1) WO2005006207A2 (de)

Families Citing this family (51)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8942426B2 (en) * 2006-03-02 2015-01-27 Michael Bar-Am On-train rail track monitoring system
US8766995B2 (en) * 2006-04-26 2014-07-01 Qualcomm Incorporated Graphics system with configurable caches
US20070268289A1 (en) * 2006-05-16 2007-11-22 Chun Yu Graphics system with dynamic reposition of depth engine
US8884972B2 (en) 2006-05-25 2014-11-11 Qualcomm Incorporated Graphics processor with arithmetic and elementary function units
US8869147B2 (en) * 2006-05-31 2014-10-21 Qualcomm Incorporated Multi-threaded processor with deferred thread output control
US8644643B2 (en) 2006-06-14 2014-02-04 Qualcomm Incorporated Convolution filtering in a graphics processor
US8766996B2 (en) * 2006-06-21 2014-07-01 Qualcomm Incorporated Unified virtual addressed register file
US7529849B2 (en) * 2006-07-27 2009-05-05 International Business Machines Corporation Reduction of message flow between bus-connected consumers and producers
KR100867640B1 (ko) * 2007-02-06 2008-11-10 삼성전자주식회사 다중 접근 경로를 가지는 이미지 프로세싱 메모리를포함하는 시스템 온 칩
JP2008249977A (ja) * 2007-03-30 2008-10-16 Seiko Epson Corp 電気光学表示装置の描画回路、電気光学表示装置の描画方法、電気光学表示装置及び電子機器
US8260002B2 (en) * 2008-09-26 2012-09-04 Axis Ab Video analytics system, computer program product, and associated methodology for efficiently using SIMD operations
KR20100078193A (ko) * 2008-12-30 2010-07-08 주식회사 동부하이텍 슬레이브 및 그와 마스터 간의 통신 방법
US9554142B2 (en) 2011-01-28 2017-01-24 Eye IO, LLC Encoding of video stream based on scene type
WO2013100783A1 (en) * 2011-12-29 2013-07-04 Intel Corporation Method and system for control signalling in a data path module
US10331583B2 (en) 2013-09-26 2019-06-25 Intel Corporation Executing distributed memory operations using processing elements connected by distributed channels
US9262704B1 (en) * 2015-03-04 2016-02-16 Xerox Corporation Rendering images to lower bits per pixel formats using reduced numbers of registers
CA2984313C (en) * 2015-04-27 2024-03-26 First Advantage Corporation Device and method for performing validation and authentication of a physical structure or physical object
US10402168B2 (en) 2016-10-01 2019-09-03 Intel Corporation Low energy consumption mantissa multiplication for floating point multiply-add operations
US10558575B2 (en) 2016-12-30 2020-02-11 Intel Corporation Processors, methods, and systems with a configurable spatial accelerator
US10474375B2 (en) 2016-12-30 2019-11-12 Intel Corporation Runtime address disambiguation in acceleration hardware
US10572376B2 (en) 2016-12-30 2020-02-25 Intel Corporation Memory ordering in acceleration hardware
US10416999B2 (en) 2016-12-30 2019-09-17 Intel Corporation Processors, methods, and systems with a configurable spatial accelerator
US10445234B2 (en) 2017-07-01 2019-10-15 Intel Corporation Processors, methods, and systems for a configurable spatial accelerator with transactional and replay features
US10469397B2 (en) 2017-07-01 2019-11-05 Intel Corporation Processors and methods with configurable network-based dataflow operator circuits
US10467183B2 (en) 2017-07-01 2019-11-05 Intel Corporation Processors and methods for pipelined runtime services in a spatial array
US10515049B1 (en) 2017-07-01 2019-12-24 Intel Corporation Memory circuits and methods for distributed memory hazard detection and error recovery
US10445451B2 (en) 2017-07-01 2019-10-15 Intel Corporation Processors, methods, and systems for a configurable spatial accelerator with performance, correctness, and power reduction features
US10387319B2 (en) 2017-07-01 2019-08-20 Intel Corporation Processors, methods, and systems for a configurable spatial accelerator with memory system performance, power reduction, and atomics support features
US10515046B2 (en) 2017-07-01 2019-12-24 Intel Corporation Processors, methods, and systems with a configurable spatial accelerator
US10496574B2 (en) 2017-09-28 2019-12-03 Intel Corporation Processors, methods, and systems for a memory fence in a configurable spatial accelerator
US11086816B2 (en) 2017-09-28 2021-08-10 Intel Corporation Processors, methods, and systems for debugging a configurable spatial accelerator
US10445098B2 (en) 2017-09-30 2019-10-15 Intel Corporation Processors and methods for privileged configuration in a spatial array
US10380063B2 (en) 2017-09-30 2019-08-13 Intel Corporation Processors, methods, and systems with a configurable spatial accelerator having a sequencer dataflow operator
US10506161B2 (en) 2017-10-26 2019-12-10 Qualcomm Incorporated Image signal processor data traffic management
US10445250B2 (en) 2017-12-30 2019-10-15 Intel Corporation Apparatus, methods, and systems with a configurable spatial accelerator
US10417175B2 (en) 2017-12-30 2019-09-17 Intel Corporation Apparatus, methods, and systems for memory consistency in a configurable spatial accelerator
US10565134B2 (en) 2017-12-30 2020-02-18 Intel Corporation Apparatus, methods, and systems for multicast in a configurable spatial accelerator
US10564980B2 (en) 2018-04-03 2020-02-18 Intel Corporation Apparatus, methods, and systems for conditional queues in a configurable spatial accelerator
US11307873B2 (en) 2018-04-03 2022-04-19 Intel Corporation Apparatus, methods, and systems for unstructured data flow in a configurable spatial accelerator with predicate propagation and merging
US10853073B2 (en) 2018-06-30 2020-12-01 Intel Corporation Apparatuses, methods, and systems for conditional operations in a configurable spatial accelerator
US10891240B2 (en) 2018-06-30 2021-01-12 Intel Corporation Apparatus, methods, and systems for low latency communication in a configurable spatial accelerator
US11200186B2 (en) 2018-06-30 2021-12-14 Intel Corporation Apparatuses, methods, and systems for operations in a configurable spatial accelerator
US10459866B1 (en) 2018-06-30 2019-10-29 Intel Corporation Apparatuses, methods, and systems for integrated control and data processing in a configurable spatial accelerator
US10678724B1 (en) 2018-12-29 2020-06-09 Intel Corporation Apparatuses, methods, and systems for in-network storage in a configurable spatial accelerator
US10965536B2 (en) 2019-03-30 2021-03-30 Intel Corporation Methods and apparatus to insert buffers in a dataflow graph
US10817291B2 (en) 2019-03-30 2020-10-27 Intel Corporation Apparatuses, methods, and systems for swizzle operations in a configurable spatial accelerator
US10915471B2 (en) 2019-03-30 2021-02-09 Intel Corporation Apparatuses, methods, and systems for memory interface circuit allocation in a configurable spatial accelerator
US11029927B2 (en) 2019-03-30 2021-06-08 Intel Corporation Methods and apparatus to detect and annotate backedges in a dataflow graph
US11037050B2 (en) 2019-06-29 2021-06-15 Intel Corporation Apparatuses, methods, and systems for memory interface circuit arbitration in a configurable spatial accelerator
US11907713B2 (en) 2019-12-28 2024-02-20 Intel Corporation Apparatuses, methods, and systems for fused operations using sign modification in a processing element of a configurable spatial accelerator
US12086080B2 (en) 2020-09-26 2024-09-10 Intel Corporation Apparatuses, methods, and systems for a configurable accelerator having dataflow execution circuits

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5790130A (en) * 1995-06-08 1998-08-04 Hewlett-Packard Company Texel cache interrupt daemon for virtual memory management of texture maps
US20040236877A1 (en) * 1997-12-17 2004-11-25 Lee A. Burton Switch/network adapter port incorporating shared memory resources selectively accessible by a direct execution logic element and one or more dense logic devices in a fully buffered dual in-line memory module format (FB-DIMM)
US6202106B1 (en) 1998-09-09 2001-03-13 Xilinx, Inc. Method for providing specific knowledge of a structure of parameter blocks to an intelligent direct memory access controller
US6421744B1 (en) 1999-10-25 2002-07-16 Motorola, Inc. Direct memory access controller and method therefor
US6785743B1 (en) 2000-03-22 2004-08-31 University Of Washington Template data transfer coprocessor
JP2002215606A (ja) * 2001-01-24 2002-08-02 Mitsubishi Electric Corp データ処理装置
US7093104B2 (en) 2001-03-22 2006-08-15 Sony Computer Entertainment Inc. Processing modules for computer architecture for broadband networks
JP4384828B2 (ja) 2001-11-22 2009-12-16 ユニヴァーシティ オブ ワシントン コプロセッサ装置およびデータ転送を容易にするための方法
US7293155B2 (en) 2003-05-30 2007-11-06 Intel Corporation Management of access to data from memory

Also Published As

Publication number Publication date
TW200500859A (en) 2005-01-01
KR100818819B1 (ko) 2008-04-02
MY137269A (en) 2009-01-30
DE602004027493D1 (de) 2010-07-15
JP2007520767A (ja) 2007-07-26
KR20060024444A (ko) 2006-03-16
WO2005006207A2 (en) 2005-01-20
US7088371B2 (en) 2006-08-08
EP1639495A2 (de) 2006-03-29
EP1639495B1 (de) 2010-06-02
JP4344383B2 (ja) 2009-10-14
WO2005006207A3 (en) 2005-10-20
TWI269168B (en) 2006-12-21
US20040263524A1 (en) 2004-12-30

Similar Documents

Publication Publication Date Title
ATE470189T1 (de) Speicherbefehls-handler zur verwendung in einem bildsignalprozessor mit einer datengestützten architektur
SE9302399D0 (sv) Foerfarande och anordning vid tredimensionell kropp anvaendbar i maenniskokroppen
DE60006270D1 (de) Parallele prozessorarchitektur
DE60011797D1 (de) Ausführung von mehreren fäden in einem parallelprozessor
DE60009102D1 (de) Sdram-steuerungvorrichtung für parallele prozessorarchitektur
KR970012203A (ko) 트레이스 함수와 그에 따른 방법을 실행하기 위한 데이타 처리 시스템
TW364959B (en) Data processor and data processing system
DE60215810D1 (de) Verfahren und gerät zur transformation eines bildes einer biologischen oberfläche
KR970019620A (ko) 방문자 확인 시스템 및 그 방법
DE69419284D1 (de) System zur Identifikation und Steuerung eines elektrochemischen Generators
DE60228999D1 (de) Gesichtserkennung durch kernel-fisherfaces
DE60010674D1 (de) Hochgeschwindigkeits-prozessorsystem, verfahren zu dessen verwendung und aufzeichnungsmedium
ATE468562T1 (de) Virtualisierung von e/a-adapterressourcen
RU2009102657A (ru) Сегментация изображения на основе модели с переменным разрешением
EP1622066A4 (de) Etikett und verfahren und system damit
CN104985939A (zh) 一种激光打标机控制方法和激光打标机
ATE385325T1 (de) Verfahren und einrichtung zur konfiguration eines steuerungssystems
CN214475121U (zh) 神经网络模型的评估电路板
DE60044695D1 (de) Cachespeicher und System
ATE438137T1 (de) Verfahren und systeme zur datenmanipulation
CN111061902B (zh) 一种基于文本语义分析的绘图方法、装置及终端设备
Dutta Remote sensing of energy fluxes and soil moisture content
SE9303902L (sv) Anordning och förfarande vid talsyntes
Vandewalle et al. Experiences with reproducible research in various facets of signal processing research
Cragg et al. Canadian issues in environmental ethics

Legal Events

Date Code Title Description
RER Ceased as to paragraph 5 lit. 3 law introducing patent treaties