ATE463792T1 - Durch ein temperaturfeld gesteuerte regelung für verarbeitungssysteme - Google Patents
Durch ein temperaturfeld gesteuerte regelung für verarbeitungssystemeInfo
- Publication number
- ATE463792T1 ATE463792T1 AT00402948T AT00402948T ATE463792T1 AT E463792 T1 ATE463792 T1 AT E463792T1 AT 00402948 T AT00402948 T AT 00402948T AT 00402948 T AT00402948 T AT 00402948T AT E463792 T1 ATE463792 T1 AT E463792T1
- Authority
- AT
- Austria
- Prior art keywords
- level
- cache
- miss
- task
- tlb
- Prior art date
Links
Classifications
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/46—Multiprogramming arrangements
- G06F9/50—Allocation of resources, e.g. of the central processing unit [CPU]
- G06F9/5005—Allocation of resources, e.g. of the central processing unit [CPU] to service a request
- G06F9/5011—Allocation of resources, e.g. of the central processing unit [CPU] to service a request the resources being hardware resources other than CPUs, Servers and Terminals
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/16—Constructional details or arrangements
- G06F1/20—Cooling means
- G06F1/206—Cooling means comprising thermal management
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/26—Power supply means, e.g. regulation thereof
- G06F1/32—Means for saving power
- G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/26—Power supply means, e.g. regulation thereof
- G06F1/32—Means for saving power
- G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
- G06F1/3234—Power saving characterised by the action undertaken
- G06F1/329—Power saving characterised by the action undertaken by task scheduling
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/30—Monitoring
- G06F11/34—Recording or statistical evaluation of computer activity, e.g. of down time, of input/output operation ; Recording or statistical evaluation of user activity, e.g. usability assessment
- G06F11/3409—Recording or statistical evaluation of computer activity, e.g. of down time, of input/output operation ; Recording or statistical evaluation of user activity, e.g. usability assessment for performance assessment
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
- G06F12/0292—User address space allocation, e.g. contiguous or non contiguous base addressing using tables or multilevel address translation means
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0877—Cache access modes
- G06F12/0879—Burst mode
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0891—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches using clearing, invalidating or resetting means
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/10—Address translation
- G06F12/1027—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30003—Arrangements for executing specific machine instructions
- G06F9/3004—Arrangements for executing specific machine instructions to perform operations on memory
- G06F9/30043—LOAD or STORE instructions; Clear instruction
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/46—Multiprogramming arrangements
- G06F9/50—Allocation of resources, e.g. of the central processing unit [CPU]
- G06F9/5094—Allocation of resources, e.g. of the central processing unit [CPU] where the allocation takes into account power or heat criteria
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/10—Address translation
- G06F12/1081—Address translation for peripheral access to main memory, e.g. direct memory access [DMA]
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2201/00—Indexing scheme relating to error detection, to error correction, and to monitoring
- G06F2201/81—Threshold
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2201/00—Indexing scheme relating to error detection, to error correction, and to monitoring
- G06F2201/815—Virtual
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2201/00—Indexing scheme relating to error detection, to error correction, and to monitoring
- G06F2201/86—Event-based monitoring
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2201/00—Indexing scheme relating to error detection, to error correction, and to monitoring
- G06F2201/88—Monitoring involving counting
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2201/00—Indexing scheme relating to error detection, to error correction, and to monitoring
- G06F2201/885—Monitoring specific for caches
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2209/00—Indexing scheme relating to G06F9/00
- G06F2209/50—Indexing scheme relating to G06F9/50
- G06F2209/5014—Reservation
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2209/00—Indexing scheme relating to G06F9/00
- G06F2209/50—Indexing scheme relating to G06F9/50
- G06F2209/5021—Priority
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2209/00—Indexing scheme relating to G06F9/00
- G06F2209/50—Indexing scheme relating to G06F9/50
- G06F2209/507—Low-level
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
- G06F2212/10—Providing a specific technical effect
- G06F2212/1028—Power efficiency
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
- G06F2212/68—Details of translation look-aside buffer [TLB]
- G06F2212/681—Multi-level TLB, e.g. microTLB and main TLB
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Software Systems (AREA)
- Human Computer Interaction (AREA)
- Computer Hardware Design (AREA)
- Quality & Reliability (AREA)
- Memory System Of A Hierarchy Structure (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP00402331A EP1182559B1 (de) | 2000-08-21 | 2000-08-21 | Mikroprozessor |
Publications (1)
Publication Number | Publication Date |
---|---|
ATE463792T1 true ATE463792T1 (de) | 2010-04-15 |
Family
ID=8173823
Family Applications (8)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
AT00402948T ATE463792T1 (de) | 2000-08-21 | 2000-10-24 | Durch ein temperaturfeld gesteuerte regelung für verarbeitungssysteme |
AT00402947T ATE440328T1 (de) | 2000-08-21 | 2000-10-24 | Auf aufgaben basierte adaptive profilerstellung und fehlerbeseitigung |
AT01400684T ATE527599T1 (de) | 2000-08-21 | 2001-03-15 | Cache-speicher mit blockvorausholung und dma |
AT01400686T ATE441893T1 (de) | 2000-08-21 | 2001-03-15 | Cache-speicher mit dma und schmutzigen bits |
AT01400685T ATE509315T1 (de) | 2000-08-21 | 2001-03-22 | Intelligenter cache-speicher mit unterbrechbarer blockvorausholung |
AT01401216T ATE500552T1 (de) | 2000-08-21 | 2001-05-11 | Tlb-ver- und entriegelungsoperation |
AT01401218T ATE497211T1 (de) | 2000-08-21 | 2001-05-11 | Auf gemeinsamem bit basierte tlb-operationen |
AT01401678T ATE546778T1 (de) | 2000-08-21 | 2001-06-25 | Auf id aufgaben basierende fehlerverwaltung und - beseitigung |
Family Applications After (7)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
AT00402947T ATE440328T1 (de) | 2000-08-21 | 2000-10-24 | Auf aufgaben basierte adaptive profilerstellung und fehlerbeseitigung |
AT01400684T ATE527599T1 (de) | 2000-08-21 | 2001-03-15 | Cache-speicher mit blockvorausholung und dma |
AT01400686T ATE441893T1 (de) | 2000-08-21 | 2001-03-15 | Cache-speicher mit dma und schmutzigen bits |
AT01400685T ATE509315T1 (de) | 2000-08-21 | 2001-03-22 | Intelligenter cache-speicher mit unterbrechbarer blockvorausholung |
AT01401216T ATE500552T1 (de) | 2000-08-21 | 2001-05-11 | Tlb-ver- und entriegelungsoperation |
AT01401218T ATE497211T1 (de) | 2000-08-21 | 2001-05-11 | Auf gemeinsamem bit basierte tlb-operationen |
AT01401678T ATE546778T1 (de) | 2000-08-21 | 2001-06-25 | Auf id aufgaben basierende fehlerverwaltung und - beseitigung |
Country Status (4)
Country | Link |
---|---|
US (1) | US6751706B2 (de) |
EP (1) | EP1182559B1 (de) |
AT (8) | ATE463792T1 (de) |
DE (6) | DE60041444D1 (de) |
Families Citing this family (116)
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2000
- 2000-08-21 DE DE60041444T patent/DE60041444D1/de not_active Expired - Lifetime
- 2000-08-21 EP EP00402331A patent/EP1182559B1/de not_active Expired - Lifetime
- 2000-10-24 AT AT00402948T patent/ATE463792T1/de not_active IP Right Cessation
- 2000-10-24 DE DE60044128T patent/DE60044128D1/de not_active Expired - Lifetime
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- 2000-10-24 DE DE60042780T patent/DE60042780D1/de not_active Expired - Lifetime
-
2001
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- 2001-03-22 AT AT01400685T patent/ATE509315T1/de not_active IP Right Cessation
- 2001-05-11 DE DE60144131T patent/DE60144131D1/de not_active Expired - Lifetime
- 2001-05-11 AT AT01401216T patent/ATE500552T1/de not_active IP Right Cessation
- 2001-05-11 AT AT01401218T patent/ATE497211T1/de not_active IP Right Cessation
- 2001-05-11 DE DE60143929T patent/DE60143929D1/de not_active Expired - Lifetime
- 2001-06-25 AT AT01401678T patent/ATE546778T1/de active
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Also Published As
Publication number | Publication date |
---|---|
US6751706B2 (en) | 2004-06-15 |
DE60143929D1 (de) | 2011-03-10 |
DE60144131D1 (de) | 2011-04-14 |
DE60139748D1 (de) | 2009-10-15 |
ATE500552T1 (de) | 2011-03-15 |
DE60044128D1 (de) | 2010-05-20 |
EP1182559B1 (de) | 2009-01-21 |
ATE441893T1 (de) | 2009-09-15 |
ATE509315T1 (de) | 2011-05-15 |
ATE440328T1 (de) | 2009-09-15 |
ATE527599T1 (de) | 2011-10-15 |
ATE546778T1 (de) | 2012-03-15 |
US20020073282A1 (en) | 2002-06-13 |
DE60042780D1 (de) | 2009-10-01 |
DE60041444D1 (de) | 2009-03-12 |
EP1182559A1 (de) | 2002-02-27 |
ATE497211T1 (de) | 2011-02-15 |
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