ATE453154T1 - Schaltmatrixarchitektur eines gemeinsamen speichers - Google Patents

Schaltmatrixarchitektur eines gemeinsamen speichers

Info

Publication number
ATE453154T1
ATE453154T1 AT06717512T AT06717512T ATE453154T1 AT E453154 T1 ATE453154 T1 AT E453154T1 AT 06717512 T AT06717512 T AT 06717512T AT 06717512 T AT06717512 T AT 06717512T AT E453154 T1 ATE453154 T1 AT E453154T1
Authority
AT
Austria
Prior art keywords
ports
memory
data rate
receive
data
Prior art date
Application number
AT06717512T
Other languages
English (en)
Inventor
Uri Cummings
Andrew Lines
Patrick Pelletier
Robert Southworth
Original Assignee
Fulcrum Microsystems Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fulcrum Microsystems Inc filed Critical Fulcrum Microsystems Inc
Application granted granted Critical
Publication of ATE453154T1 publication Critical patent/ATE453154T1/de

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1048—Data bus control circuits, e.g. precharging, presetting, equalising
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1075—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers for multiport memories each having random access ports and serial ports, e.g. video RAM
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/10—Packet switching elements characterised by the switching fabric construction
    • H04L49/103—Packet switching elements characterised by the switching fabric construction using a shared central buffer; using a shared memory
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/10—Packet switching elements characterised by the switching fabric construction
    • H04L49/101—Packet switching elements characterised by the switching fabric construction using crossbar or matrix
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/35—Switches specially adapted for specific applications
    • H04L49/351—Switches specially adapted for specific applications for local area network [LAN], e.g. Ethernet switches

Landscapes

  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)
  • Multi Processors (AREA)
  • Use Of Switch Circuits For Exchanges And Methods Of Control Of Multiplex Exchanges (AREA)
  • Electronic Switches (AREA)
AT06717512T 2005-01-12 2006-01-05 Schaltmatrixarchitektur eines gemeinsamen speichers ATE453154T1 (de)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US64379405P 2005-01-12 2005-01-12
US11/208,451 US7814280B2 (en) 2005-01-12 2005-08-18 Shared-memory switch fabric architecture
PCT/US2006/000326 WO2006076204A2 (en) 2005-01-12 2006-01-05 Shared-memory switch fabric architecture

Publications (1)

Publication Number Publication Date
ATE453154T1 true ATE453154T1 (de) 2010-01-15

Family

ID=36654613

Family Applications (1)

Application Number Title Priority Date Filing Date
AT06717512T ATE453154T1 (de) 2005-01-12 2006-01-05 Schaltmatrixarchitektur eines gemeinsamen speichers

Country Status (6)

Country Link
US (2) US7814280B2 (de)
EP (1) EP1839166B1 (de)
JP (1) JP4667469B2 (de)
AT (1) ATE453154T1 (de)
DE (1) DE602006011272D1 (de)
WO (1) WO2006076204A2 (de)

Families Citing this family (42)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040085904A1 (en) * 2002-10-31 2004-05-06 Bordogna Mark A. Method for flow control of packets aggregated from multiple logical ports over a transport link
EP1987428A2 (de) * 2006-02-24 2008-11-05 Mbda Uk Limited Verteilte echtzeit-prozessorumgebung
US7280398B1 (en) * 2006-08-31 2007-10-09 Micron Technology, Inc. System and memory for sequential multi-plane page memory operations
US20080155187A1 (en) * 2006-12-20 2008-06-26 Maurizio Skerlj System including memory buffer configured to decouple data rates
US7916718B2 (en) * 2007-04-19 2011-03-29 Fulcrum Microsystems, Inc. Flow and congestion control in switch architectures for multi-hop, memory efficient fabrics
US20090019184A1 (en) * 2007-07-10 2009-01-15 Qimonda Ag Interfacing memory devices
US8356138B1 (en) * 2007-08-20 2013-01-15 Xilinx, Inc. Methods for implementing programmable memory controller for distributed DRAM system-in-package (SiP)
US20090063807A1 (en) * 2007-08-29 2009-03-05 International Business Machines Corporation Data redistribution in shared nothing architecture
EP2068561A1 (de) 2007-11-29 2009-06-10 Deutsche Thomson OHG Verfahren und Vorrichtung zur Aufzeichnung von Rahmen
US8370557B2 (en) * 2008-12-19 2013-02-05 Intel Corporation Pseudo dual-port SRAM and a shared memory switch using multiple memory banks and a sideband memory
US8126002B2 (en) * 2009-03-31 2012-02-28 Juniper Networks, Inc. Methods and apparatus related to a shared memory buffer for variable-sized cells
US8644140B2 (en) * 2009-09-09 2014-02-04 Mellanox Technologies Ltd. Data switch with shared port buffers
US8873377B2 (en) 2009-11-18 2014-10-28 Juniper Networks, Inc. Method and apparatus for hitless failover in networking systems using single database
JP5333200B2 (ja) * 2009-12-25 2013-11-06 富士通株式会社 パケット通信制御装置、メモリアクセス制御装置及び情報処理システム
US8441922B1 (en) * 2010-10-05 2013-05-14 Qlogic, Corporation Method and system for congestion management in networks
US8699491B2 (en) 2011-07-25 2014-04-15 Mellanox Technologies Ltd. Network element with shared buffers
KR101292309B1 (ko) * 2011-12-27 2013-07-31 숭실대학교산학협력단 반도체칩 및 메모리 제어방법, 그리고 그 방법을 컴퓨터에서 실행시키기 위한 프로그램을 기록한 기록매체
WO2013167973A2 (en) * 2012-05-10 2013-11-14 Marvell World Trade Ltd. Hybrid dataflow processor
US9438537B2 (en) 2012-07-03 2016-09-06 Freescale Semiconductor, Inc. Method for cut through forwarding data packets between electronic communication devices
US9582440B2 (en) 2013-02-10 2017-02-28 Mellanox Technologies Ltd. Credit based low-latency arbitration with data transfer
US8989011B2 (en) 2013-03-14 2015-03-24 Mellanox Technologies Ltd. Communication over multiple virtual lanes using a shared buffer
US9189435B2 (en) * 2013-04-23 2015-11-17 Apple Inc. Method and apparatus for arbitration with multiple source paths
US9535832B2 (en) * 2013-04-30 2017-01-03 Mediatek Singapore Pte. Ltd. Multi-hierarchy interconnect system and method for cache system
US9641465B1 (en) 2013-08-22 2017-05-02 Mellanox Technologies, Ltd Packet switch with reduced latency
US9548960B2 (en) 2013-10-06 2017-01-17 Mellanox Technologies Ltd. Simplified packet routing
US9325641B2 (en) 2014-03-13 2016-04-26 Mellanox Technologies Ltd. Buffering schemes for communication over long haul links
KR102106261B1 (ko) 2014-06-17 2020-05-04 삼성전자주식회사 메모리 컨트롤러의 작동 방법과 이를 포함하는 장치들의 작동 방법들
US9584429B2 (en) 2014-07-21 2017-02-28 Mellanox Technologies Ltd. Credit based flow control for long-haul links
CN104852863B (zh) * 2015-04-15 2018-04-10 清华大学 一种共享缓存交换机中的动态阈值管理方法及装置
US10326606B2 (en) * 2016-02-18 2019-06-18 Media Links Co., Ltd. Multicast switching system
US10277533B2 (en) * 2016-11-18 2019-04-30 International Business Machines Corporation Cut-through bridge error isolation
US10176857B1 (en) * 2017-06-22 2019-01-08 Globalfoundries Inc. Read and write scheme for high density SRAM
US11489789B2 (en) * 2018-06-29 2022-11-01 Intel Corporation Technologies for adaptive network packet egress scheduling
US10951549B2 (en) 2019-03-07 2021-03-16 Mellanox Technologies Tlv Ltd. Reusing switch ports for external buffer network
US11171884B2 (en) 2019-03-13 2021-11-09 Mellanox Technologies Tlv Ltd. Efficient memory utilization and egress queue fairness
US11470010B2 (en) 2020-02-06 2022-10-11 Mellanox Technologies, Ltd. Head-of-queue blocking for multiple lossless queues
US11558316B2 (en) 2021-02-15 2023-01-17 Mellanox Technologies, Ltd. Zero-copy buffering of traffic of long-haul links
US12474833B2 (en) 2021-11-02 2025-11-18 Mellanox Technologies, Ltd Queue bandwidth estimation for management of shared buffers and allowing visibility of shared buffer status
JP7537769B2 (ja) 2022-01-12 2024-08-21 Ｎｅｃプラットフォームズ株式会社 シリアルインタフェース回路、その制御方法、プログラム、通信モジュール及び通信装置
US11973696B2 (en) 2022-01-31 2024-04-30 Mellanox Technologies, Ltd. Allocation of shared reserve memory to queues in a network device
US11876726B2 (en) * 2022-03-07 2024-01-16 Nxp B.V. Disabling cut-through frame transfer based on a cycle time period and apparatus for disabling
US12375404B2 (en) 2022-08-25 2025-07-29 Mellanox Technologies, Ltd Flow-based congestion control

Family Cites Families (55)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4680701A (en) * 1984-04-11 1987-07-14 Texas Instruments Incorporated Asynchronous high speed processor having high speed memories with domino circuits contained therein
GB8711991D0 (en) * 1987-05-21 1987-06-24 British Aerospace Asynchronous communication systems
US4912348A (en) * 1988-12-09 1990-03-27 Idaho Research Foundation Method for designing pass transistor asynchronous sequential circuits
US5752070A (en) * 1990-03-19 1998-05-12 California Institute Of Technology Asynchronous processors
JP2583679B2 (ja) * 1990-07-06 1997-02-19 三菱電機株式会社 セル交換装置
US5121003A (en) 1990-10-10 1992-06-09 Hal Computer Systems, Inc. Zero overhead self-timed iterative logic
US5434520A (en) * 1991-04-12 1995-07-18 Hewlett-Packard Company Clocking systems and methods for pipelined self-timed dynamic logic circuits
US5367638A (en) * 1991-12-23 1994-11-22 U.S. Philips Corporation Digital data processing circuit with control of data flow by control of the supply voltage
DE4214981A1 (de) * 1992-05-06 1993-11-11 Siemens Ag Asynchrone Logikschaltung für den 2-Phasen-Betrieb
DE69430352T2 (de) * 1993-10-21 2003-01-30 Sun Microsystems Inc., Mountain View Gegenflusspipeline
US5440182A (en) * 1993-10-22 1995-08-08 The Board Of Trustees Of The Leland Stanford Junior University Dynamic logic interconnect speed-up circuit
US6152613A (en) * 1994-07-08 2000-11-28 California Institute Of Technology Circuit implementations for asynchronous processors
US5642501A (en) * 1994-07-26 1997-06-24 Novell, Inc. Computer method and apparatus for asynchronous ordered operations
US5732233A (en) * 1995-01-23 1998-03-24 International Business Machines Corporation High speed pipeline method and apparatus
DE69621763T2 (de) * 1995-08-23 2003-02-06 Koninklijke Philips Electronics N.V., Eindhoven Datenverarbeitungssystem mit einer asynchrongesteuerten pipeline
EP0882357B1 (de) * 1996-01-03 2004-07-21 Sony Electronics, Inc. Kopiergeschütztes aufnahme- und wiedergabesystem
JP3156752B2 (ja) * 1996-02-09 2001-04-16 日本電気株式会社 Ａｔｍスイッチ装置及びその制御方法
GB2310738B (en) * 1996-02-29 2000-02-16 Advanced Risc Mach Ltd Dynamic logic pipeline control
US5864539A (en) * 1996-05-06 1999-01-26 Bay Networks, Inc. Method and apparatus for a rate-based congestion control in a shared memory switch
US5889979A (en) 1996-05-24 1999-03-30 Hewlett-Packard, Co. Transparent data-triggered pipeline latch
US5894481A (en) * 1996-09-11 1999-04-13 Mcdata Corporation Fiber channel switch employing distributed queuing
US6289021B1 (en) * 1997-01-24 2001-09-11 Interactic Holdings, Llc Scaleable low-latency switch for usage in an interconnect structure
US6160813A (en) * 1997-03-21 2000-12-12 Brocade Communications Systems, Inc. Fibre channel switching system and method
US6381692B1 (en) * 1997-07-16 2002-04-30 California Institute Of Technology Pipelined asynchronous processing
US5920899A (en) * 1997-09-02 1999-07-06 Acorn Networks, Inc. Asynchronous pipeline whose stages generate output request before latching data
US6502180B1 (en) * 1997-09-12 2002-12-31 California Institute Of Technology Asynchronous circuits with pipelined completion process
US6038656A (en) * 1997-09-12 2000-03-14 California Institute Of Technology Pipelined completion for asynchronous communication
US6301655B1 (en) * 1997-09-15 2001-10-09 California Institute Of Technology Exception processing in asynchronous processor
US5949259A (en) * 1997-11-19 1999-09-07 Atmel Corporation Zero-delay slew-rate controlled output buffer
US5973512A (en) * 1997-12-02 1999-10-26 National Semiconductor Corporation CMOS output buffer having load independent slewing
US6456590B1 (en) * 1998-02-13 2002-09-24 Texas Instruments Incorporated Static and dynamic flow control using virtual input queueing for shared memory ethernet switches
US7002982B1 (en) * 1998-07-08 2006-02-21 Broadcom Corporation Apparatus and method for storing data
US6625159B1 (en) * 1998-11-30 2003-09-23 Hewlett-Packard Development Company, L.P. Nonblocking and fair queuing switching method and shared memory packet switch
US7120117B1 (en) * 2000-08-29 2006-10-10 Broadcom Corporation Starvation free flow control in a shared memory switching device
US6295571B1 (en) * 1999-03-19 2001-09-25 Times N Systems, Inc. Shared memory apparatus and method for multiprocessor systems
US6678277B1 (en) * 1999-11-09 2004-01-13 3Com Corporation Efficient means to provide back pressure without head of line blocking in a virtual output queued forwarding system
US7028134B2 (en) * 1999-12-30 2006-04-11 Conexant Systems, Inc. Crossbar integrated circuit with parallel channels for a communication device
US6657962B1 (en) * 2000-04-10 2003-12-02 International Business Machines Corporation Method and system for managing congestion in a network
US6535510B2 (en) * 2000-06-19 2003-03-18 Broadcom Corporation Switch fabric with path redundancy
US20020136229A1 (en) * 2001-01-09 2002-09-26 Lucent Technologies, Inc. Non-blocking crossbar and method of operation thereof
US6594234B1 (en) * 2001-05-31 2003-07-15 Fujitsu Network Communications, Inc. System and method for scheduling traffic for different classes of service
US7054312B2 (en) * 2001-08-17 2006-05-30 Mcdata Corporation Multi-rate shared memory architecture for frame storage and switching
US7099275B2 (en) * 2001-09-21 2006-08-29 Slt Logic Llc Programmable multi-service queue scheduler
US20030088694A1 (en) * 2001-11-02 2003-05-08 Internet Machines Corporation Multicasting method and switch
WO2003043272A1 (en) 2001-11-13 2003-05-22 Transwitch Corporation Overcoming access latency inefficiency in memories for packet switched networks
KR100429897B1 (ko) * 2001-12-13 2004-05-03 한국전자통신연구원 공유 버퍼형 스위치의 적응 버퍼 배분 방법 및 이에사용되는 스위치
US7298739B1 (en) * 2001-12-14 2007-11-20 Applied Micro Circuits Corporation System and method for communicating switch fabric control information
US7283557B2 (en) * 2002-01-25 2007-10-16 Fulcrum Microsystems, Inc. Asynchronous crossbar with deterministic or arbitrated control
US6950959B2 (en) * 2002-02-12 2005-09-27 Fulcrum Microystems Inc. Techniques for facilitating conversion between asynchronous and synchronous domains
US20040151184A1 (en) * 2002-12-13 2004-08-05 Zarlink Semiconductor V.N. Inc. Class-based rate control using multi-threshold leaky bucket
US7650413B2 (en) * 2003-02-07 2010-01-19 Fujitsu Limited Managing shared memory resources in a high-speed switching environment
KR100735408B1 (ko) * 2003-03-10 2007-07-04 삼성전자주식회사 이더넷 기반의 네트워크에서 서비스 클래스별 트래픽의스위칭 제어 방법 및 그 스위칭 장치
US7149996B1 (en) * 2003-07-11 2006-12-12 Xilinx, Inc. Reconfigurable multi-stage crossbar
ATE452408T1 (de) * 2003-07-14 2010-01-15 Fulcrum Microsystems Inc Asynchroner statischer direktzugriffspeicher
US7394808B2 (en) * 2004-05-24 2008-07-01 Nortel Networks Limited Method and apparatus for implementing scheduling algorithms in a network element

Also Published As

Publication number Publication date
JP2008527922A (ja) 2008-07-24
JP4667469B2 (ja) 2011-04-13
US20060155938A1 (en) 2006-07-13
US20100325370A1 (en) 2010-12-23
EP1839166A2 (de) 2007-10-03
US7814280B2 (en) 2010-10-12
EP1839166A4 (de) 2009-03-04
WO2006076204A3 (en) 2007-10-04
DE602006011272D1 (de) 2010-02-04
WO2006076204A2 (en) 2006-07-20
EP1839166B1 (de) 2009-12-23

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