ATE450002T1 - Verteilte schleifensteuerungsarchitektur für mehrfach-threads in einfach-thread-prozessoren - Google Patents

Verteilte schleifensteuerungsarchitektur für mehrfach-threads in einfach-thread-prozessoren

Info

Publication number
ATE450002T1
ATE450002T1 AT06829300T AT06829300T ATE450002T1 AT E450002 T1 ATE450002 T1 AT E450002T1 AT 06829300 T AT06829300 T AT 06829300T AT 06829300 T AT06829300 T AT 06829300T AT E450002 T1 ATE450002 T1 AT E450002T1
Authority
AT
Austria
Prior art keywords
loops
threads
loop control
control architecture
distributed loop
Prior art date
Application number
AT06829300T
Other languages
English (en)
Inventor
Murali Jayapala
Praveen Raghavan
Franky Catthoor
Original Assignee
Imec
Univ Leuven Kath
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Imec, Univ Leuven Kath filed Critical Imec
Application granted granted Critical
Publication of ATE450002T1 publication Critical patent/ATE450002T1/de

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3802—Instruction prefetching
    • G06F9/3808—Instruction prefetching for instruction reuse, e.g. trace cache, branch target cache
    • G06F9/381—Loop buffering
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/32—Address formation of the next instruction, e.g. by incrementing the instruction counter
    • G06F9/322—Address formation of the next instruction, e.g. by incrementing the instruction counter for non-sequential address
    • G06F9/325—Address formation of the next instruction, e.g. by incrementing the instruction counter for non-sequential address for loops, e.g. loop detection or loop counter
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3851—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution from multiple instruction streams, e.g. multistreaming
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3885—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3885—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units
    • G06F9/3889—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units controlled by multiple instructions, e.g. MIMD, decoupled access or execute
    • G06F9/3891—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units controlled by multiple instructions, e.g. MIMD, decoupled access or execute organised in groups of units sharing resources, e.g. clusters

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Multimedia (AREA)
  • Executing Machine-Instructions (AREA)
  • Multi Processors (AREA)
  • Memory System (AREA)
  • Polishing Bodies And Polishing Tools (AREA)
  • Advance Control (AREA)
  • Superconductors And Manufacturing Methods Therefor (AREA)
  • Amplifiers (AREA)
  • Secondary Cells (AREA)
AT06829300T 2005-12-05 2006-12-05 Verteilte schleifensteuerungsarchitektur für mehrfach-threads in einfach-thread-prozessoren ATE450002T1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
GBGB0524720.0A GB0524720D0 (en) 2005-12-05 2005-12-05 Ultra low power ASIP architecture II
PCT/EP2006/011655 WO2007065627A2 (en) 2005-12-05 2006-12-05 Distributed loop controller architecture for multi-threading in uni-threaded processors

Publications (1)

Publication Number Publication Date
ATE450002T1 true ATE450002T1 (de) 2009-12-15

Family

ID=35686041

Family Applications (1)

Application Number Title Priority Date Filing Date
AT06829300T ATE450002T1 (de) 2005-12-05 2006-12-05 Verteilte schleifensteuerungsarchitektur für mehrfach-threads in einfach-thread-prozessoren

Country Status (6)

Country Link
US (1) US20080294882A1 (de)
EP (1) EP1958059B1 (de)
AT (1) ATE450002T1 (de)
DE (1) DE602006010733D1 (de)
GB (1) GB0524720D0 (de)
WO (1) WO2007065627A2 (de)

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US10621092B2 (en) 2008-11-24 2020-04-14 Intel Corporation Merging level cache and data cache units having indicator bits related to speculative execution
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US8584103B2 (en) 2010-06-17 2013-11-12 International Business Machines Corporation Reducing parallelism of computer source code
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US8479042B1 (en) * 2010-11-01 2013-07-02 Xilinx, Inc. Transaction-level lockstep
EP2737407B1 (de) 2011-07-26 2021-04-28 IMEC vzw Verfahren und vorrichtung zur reduzierung von leckagen und für dynamischen energieverbrauch in hochgeschwindigkeitsspeichern
US9417855B2 (en) 2011-09-30 2016-08-16 Intel Corporation Instruction and logic to perform dynamic binary translation
US10228679B2 (en) * 2011-11-11 2019-03-12 Rockwell Automation Technologies, Inc. Control environment command execution
EP2608015B1 (de) * 2011-12-21 2019-02-06 IMEC vzw System und Verfahren zur Ausführung einer Multiplikation
CN104303168B (zh) * 2012-04-25 2016-12-07 英派尔科技开发有限公司 用于灵活资源需求应用的认证
US9292569B2 (en) * 2012-10-02 2016-03-22 Oracle International Corporation Semi-join acceleration
KR102062208B1 (ko) * 2013-05-03 2020-02-11 삼성전자주식회사 멀티스레드 프로그램 코드의 변환 장치 및 방법
US9891936B2 (en) 2013-09-27 2018-02-13 Intel Corporation Method and apparatus for page-level monitoring
KR102384347B1 (ko) 2015-05-26 2022-04-07 삼성전자주식회사 클록 관리 유닛을 포함하는 시스템 온 칩 및 그 동작방법
DE102016109387A1 (de) 2015-05-26 2016-12-01 Samsung Electronics Co., Ltd. Ein-Chip-System mit Taktverwaltungseinheit und Verfahren zum Betreiben des Ein-Chip-Systems
EP3144820A1 (de) 2015-09-18 2017-03-22 Stichting IMEC Nederland Netzwerk zur übertragung von daten zwischen clustern für eine dynamisch geteilte kommunikationsplattform
US10789055B2 (en) * 2015-10-05 2020-09-29 Reservoir Labs, Inc. Systems and methods for scalable hierarchical polyhedral compilation
US9928117B2 (en) 2015-12-11 2018-03-27 Vivante Corporation Hardware access counters and event generation for coordinating multithreaded processing
US10241794B2 (en) 2016-12-27 2019-03-26 Intel Corporation Apparatus and methods to support counted loop exits in a multi-strand loop processor
US20180181398A1 (en) * 2016-12-28 2018-06-28 Intel Corporation Apparatus and methods of decomposing loops to improve performance and power efficiency
EP3432226B1 (de) 2017-07-19 2023-11-01 IMEC vzw Steuerungsebenenorganisation für flexible digitale datenebene
GB2580316B (en) * 2018-12-27 2021-02-24 Graphcore Ltd Instruction cache in a multi-threaded processor
KR20210046348A (ko) * 2019-10-18 2021-04-28 삼성전자주식회사 복수의 프로세서들에 유연하게 메모리를 할당하기 위한 메모리 시스템 및 그것의 동작 방법

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Also Published As

Publication number Publication date
DE602006010733D1 (de) 2010-01-07
GB0524720D0 (en) 2006-01-11
EP1958059B1 (de) 2009-11-25
WO2007065627A2 (en) 2007-06-14
WO2007065627A3 (en) 2007-07-19
US20080294882A1 (en) 2008-11-27
EP1958059A2 (de) 2008-08-20

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