ATE434220T1 - Datenübertragungssteuerungsgerät mit mehreren toren - Google Patents

Datenübertragungssteuerungsgerät mit mehreren toren

Info

Publication number
ATE434220T1
ATE434220T1 AT00202513T AT00202513T ATE434220T1 AT E434220 T1 ATE434220 T1 AT E434220T1 AT 00202513 T AT00202513 T AT 00202513T AT 00202513 T AT00202513 T AT 00202513T AT E434220 T1 ATE434220 T1 AT E434220T1
Authority
AT
Austria
Prior art keywords
data
destination port
transfer
transfer controller
port
Prior art date
Application number
AT00202513T
Other languages
German (de)
English (en)
Inventor
Iain Robertson
Original Assignee
Texas Instruments Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Texas Instruments Inc filed Critical Texas Instruments Inc
Application granted granted Critical
Publication of ATE434220T1 publication Critical patent/ATE434220T1/de

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/163—Interprocessor communication
    • G06F15/17—Interprocessor communication using an input/output type connection, e.g. channel, I/O port

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Multi Processors (AREA)
  • Small-Scale Networks (AREA)
  • Communication Control (AREA)
  • Saccharide Compounds (AREA)
AT00202513T 1999-07-16 2000-07-14 Datenübertragungssteuerungsgerät mit mehreren toren ATE434220T1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
GB9916706A GB2352145A (en) 1999-07-16 1999-07-16 Prevention of bottlenecking in data transfers

Publications (1)

Publication Number Publication Date
ATE434220T1 true ATE434220T1 (de) 2009-07-15

Family

ID=10857363

Family Applications (1)

Application Number Title Priority Date Filing Date
AT00202513T ATE434220T1 (de) 1999-07-16 2000-07-14 Datenübertragungssteuerungsgerät mit mehreren toren

Country Status (6)

Country Link
US (1) US6904474B1 (enExample)
EP (1) EP1069511B1 (enExample)
JP (1) JP2001067298A (enExample)
AT (1) ATE434220T1 (enExample)
DE (1) DE60042383D1 (enExample)
GB (1) GB2352145A (enExample)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20040010609A (ko) * 2001-03-16 2004-01-31 오티쥐 소프트웨어, 인코퍼레이션 네트워크 파일 공유 방법 및 시스템
US20060064535A1 (en) * 2004-09-22 2006-03-23 Walker Robert M Efficient multi-bank memory queuing system
US7716388B2 (en) * 2005-05-13 2010-05-11 Texas Instruments Incorporated Command re-ordering in hub interface unit based on priority
US7822891B2 (en) * 2006-06-13 2010-10-26 Broadcom Corporation System and method for transferring a multidimensional array of data to a non-contiguous buffer
FR2996091B1 (fr) * 2012-09-21 2015-07-17 Thales Sa Noeud fonctionnel pour un reseau de transmission d'informations et reseau correspondant
US12164796B2 (en) * 2020-12-16 2024-12-10 Kioxia Corporation Systems and methods for data copy offload for storage devices
US11637784B2 (en) * 2021-03-31 2023-04-25 Nxp Usa, Inc. Method and system for effective use of internal and external memory for packet buffering within a network device
US12131067B2 (en) 2021-11-19 2024-10-29 Rambus Inc. Multiple host memory controller

Family Cites Families (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4887076A (en) * 1987-10-16 1989-12-12 Digital Equipment Corporation Computer interconnect coupler for clusters of data processing devices
US5036459A (en) * 1989-03-09 1991-07-30 U.S. Philips Corporation Multi-processor computer system with distributed memory and an interprocessor communication mechanism, and method for operating such mechanism
AU647535B2 (en) * 1990-09-28 1994-03-24 Fujitsu Limited Message control system in a data communication system
US5333276A (en) * 1991-12-27 1994-07-26 Intel Corporation Method and apparatus for priority selection of commands
US5629950A (en) * 1992-04-24 1997-05-13 Digital Equipment Corporation Fault management scheme for a cache memory
WO1995020191A1 (en) * 1994-01-25 1995-07-27 Apple Computer, Inc. System and method for coordinating access to a bus
US5619544A (en) * 1994-06-03 1997-04-08 Texas Instruments Incorporated Universal asynchronous receive/transmit circuit with flow control
US5581790A (en) * 1994-06-07 1996-12-03 Unisys Corporation Data feeder control system for performing data integrity check while transferring predetermined number of blocks with variable bytes through a selected one of many channels
US5924112A (en) * 1995-09-11 1999-07-13 Madge Networks Limited Bridge device
US5687390A (en) * 1995-11-14 1997-11-11 Eccs, Inc. Hierarchical queues within a storage array (RAID) controller
US5850571A (en) * 1996-04-22 1998-12-15 National Instruments Corporation System and method for converting read cycles into write cycles for improved system performance
US5894481A (en) * 1996-09-11 1999-04-13 Mcdata Corporation Fiber channel switch employing distributed queuing
US6493347B2 (en) * 1996-12-16 2002-12-10 Juniper Networks, Inc. Memory organization in a switching device
US6098109A (en) * 1996-12-30 2000-08-01 Compaq Computer Corporation Programmable arbitration system for determining priority of the ports of a network switch
US5909594A (en) * 1997-02-24 1999-06-01 Silicon Graphics, Inc. System for communications where first priority data transfer is not disturbed by second priority data transfer and where allocated bandwidth is removed when process terminates abnormally
JPH10254843A (ja) * 1997-03-06 1998-09-25 Hitachi Ltd クロスバスイッチ、該クロスバスイッチを備えた並列計算機及びブロードキャスト通信方法
JP3529588B2 (ja) * 1997-05-30 2004-05-24 インターナショナル・ビジネス・マシーンズ・コーポレーション 計算機ネットワーク・システム、計算機、一時保管用計算機及びこれらにおける方法
US6606326B1 (en) * 1999-07-02 2003-08-12 International Business Machines Corporation Packet switch employing dynamic transfer of data packet from central shared queue path to cross-point switching matrix path
US6629166B1 (en) * 2000-06-29 2003-09-30 Intel Corporation Methods and systems for efficient connection of I/O devices to a channel-based switched fabric

Also Published As

Publication number Publication date
EP1069511A3 (en) 2006-04-05
DE60042383D1 (de) 2009-07-30
GB9916706D0 (en) 1999-09-15
US6904474B1 (en) 2005-06-07
JP2001067298A (ja) 2001-03-16
EP1069511A2 (en) 2001-01-17
GB2352145A (en) 2001-01-17
EP1069511B1 (en) 2009-06-17

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Legal Events

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RER Ceased as to paragraph 5 lit. 3 law introducing patent treaties