ATE432500T1 - System, verfahren und anordnung einer flexiblen dram architektur - Google Patents
System, verfahren und anordnung einer flexiblen dram architekturInfo
- Publication number
- ATE432500T1 ATE432500T1 AT03765490T AT03765490T ATE432500T1 AT E432500 T1 ATE432500 T1 AT E432500T1 AT 03765490 T AT03765490 T AT 03765490T AT 03765490 T AT03765490 T AT 03765490T AT E432500 T1 ATE432500 T1 AT E432500T1
- Authority
- AT
- Austria
- Prior art keywords
- arrangement
- dram architecture
- flexible
- flexible dram
- architecture
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/06—Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
- G11C7/1045—Read-write mode select circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/408—Address circuits
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Dram (AREA)
- Executing Machine-Instructions (AREA)
- Semiconductor Memories (AREA)
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US10/199,578 US20040015645A1 (en) | 2002-07-19 | 2002-07-19 | System, apparatus, and method for a flexible DRAM architecture |
| PCT/US2003/021133 WO2004010435A2 (en) | 2002-07-19 | 2003-07-03 | A system, apparatus, and method for a flexible dram architecture |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| ATE432500T1 true ATE432500T1 (de) | 2009-06-15 |
Family
ID=30443334
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| AT03765490T ATE432500T1 (de) | 2002-07-19 | 2003-07-03 | System, verfahren und anordnung einer flexiblen dram architektur |
Country Status (9)
| Country | Link |
|---|---|
| US (1) | US20040015645A1 (de) |
| EP (1) | EP1523712B1 (de) |
| KR (2) | KR20050025619A (de) |
| CN (1) | CN100359492C (de) |
| AT (1) | ATE432500T1 (de) |
| AU (1) | AU2003247890A1 (de) |
| DE (1) | DE60327769D1 (de) |
| TW (1) | TWI312932B (de) |
| WO (1) | WO2004010435A2 (de) |
Families Citing this family (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7159066B2 (en) * | 2002-08-27 | 2007-01-02 | Intel Corporation | Precharge suggestion |
| US6888777B2 (en) * | 2002-08-27 | 2005-05-03 | Intel Corporation | Address decode |
| US7120765B2 (en) * | 2002-10-30 | 2006-10-10 | Intel Corporation | Memory transaction ordering |
| US7469316B2 (en) * | 2003-02-10 | 2008-12-23 | Intel Corporation | Buffered writes and memory page control |
| US7076617B2 (en) * | 2003-09-30 | 2006-07-11 | Intel Corporation | Adaptive page management |
| CN101216751B (zh) * | 2008-01-21 | 2010-07-14 | 戴葵 | 基于分布存储结构的具有数据处理能力的动态随机存储器装置 |
| CN101221532B (zh) * | 2008-01-21 | 2010-06-09 | 戴葵 | 实现具有数据处理能力的动态随机存储器的接口方法 |
Family Cites Families (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4700330A (en) * | 1985-10-30 | 1987-10-13 | Digital Equipment Corporation | Memory for a digital data processing system including circuit for controlling refresh operations during power-up and power-down conditions |
| US5390308A (en) * | 1992-04-15 | 1995-02-14 | Rambus, Inc. | Method and apparatus for address mapping of dynamic random access memory |
| US5278801A (en) * | 1992-08-31 | 1994-01-11 | Hewlett-Packard Company | Flexible addressing for drams |
| JP3304531B2 (ja) * | 1993-08-24 | 2002-07-22 | 富士通株式会社 | 半導体記憶装置 |
| US6347354B1 (en) * | 1997-10-10 | 2002-02-12 | Rambus Incorporated | Apparatus and method for maximizing information transfers over limited interconnect resources |
| US6137735A (en) * | 1998-10-30 | 2000-10-24 | Mosaid Technologies Incorporated | Column redundancy circuit with reduced signal path delay |
| JP2001060169A (ja) * | 1999-08-24 | 2001-03-06 | Hitachi Ltd | キャッシュコントローラ及びコンピュータシステム |
-
2002
- 2002-07-19 US US10/199,578 patent/US20040015645A1/en not_active Abandoned
-
2003
- 2003-07-03 AT AT03765490T patent/ATE432500T1/de not_active IP Right Cessation
- 2003-07-03 CN CNB038171953A patent/CN100359492C/zh not_active Expired - Fee Related
- 2003-07-03 KR KR1020057000931A patent/KR20050025619A/ko not_active Application Discontinuation
- 2003-07-03 EP EP03765490A patent/EP1523712B1/de not_active Expired - Lifetime
- 2003-07-03 KR KR1020087012963A patent/KR20080063531A/ko not_active Application Discontinuation
- 2003-07-03 AU AU2003247890A patent/AU2003247890A1/en not_active Abandoned
- 2003-07-03 WO PCT/US2003/021133 patent/WO2004010435A2/en active Search and Examination
- 2003-07-03 DE DE60327769T patent/DE60327769D1/de not_active Expired - Fee Related
- 2003-07-18 TW TW092119697A patent/TWI312932B/zh not_active IP Right Cessation
Also Published As
| Publication number | Publication date |
|---|---|
| TW200411387A (en) | 2004-07-01 |
| WO2004010435A3 (en) | 2004-04-01 |
| EP1523712A2 (de) | 2005-04-20 |
| KR20050025619A (ko) | 2005-03-14 |
| CN1669006A (zh) | 2005-09-14 |
| AU2003247890A1 (en) | 2004-02-09 |
| US20040015645A1 (en) | 2004-01-22 |
| AU2003247890A8 (en) | 2004-02-09 |
| KR20080063531A (ko) | 2008-07-04 |
| DE60327769D1 (de) | 2009-07-09 |
| EP1523712B1 (de) | 2009-05-27 |
| TWI312932B (en) | 2009-08-01 |
| CN100359492C (zh) | 2008-01-02 |
| WO2004010435A2 (en) | 2004-01-29 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| RER | Ceased as to paragraph 5 lit. 3 law introducing patent treaties |