ATE408151T1 - Verfahren und prüfschnittstelle zum überprüfen von digitalschaltungen - Google Patents

Verfahren und prüfschnittstelle zum überprüfen von digitalschaltungen

Info

Publication number
ATE408151T1
ATE408151T1 AT01933773T AT01933773T ATE408151T1 AT E408151 T1 ATE408151 T1 AT E408151T1 AT 01933773 T AT01933773 T AT 01933773T AT 01933773 T AT01933773 T AT 01933773T AT E408151 T1 ATE408151 T1 AT E408151T1
Authority
AT
Austria
Prior art keywords
buffered
circuitry
output
digital circuits
test interface
Prior art date
Application number
AT01933773T
Other languages
English (en)
Inventor
Marcus Kuegler
Ali Badiei
Original Assignee
Nxp Bv
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nxp Bv filed Critical Nxp Bv
Application granted granted Critical
Publication of ATE408151T1 publication Critical patent/ATE408151T1/de

Links

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/31712—Input or output aspects
    • G01R31/31716—Testing of input or output with loop-back
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/24—Testing correct operation
    • H04L1/242—Testing correct operation by comparing a transmitted test signal with a locally generated replica
    • H04L1/243—Testing correct operation by comparing a transmitted test signal with a locally generated replica at the transmitter, using a loop-back

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Input From Keyboards Or The Like (AREA)
  • Maintenance And Management Of Digital Transmission (AREA)
AT01933773T 2000-04-05 2001-03-29 Verfahren und prüfschnittstelle zum überprüfen von digitalschaltungen ATE408151T1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
EP00201242 2000-04-05

Publications (1)

Publication Number Publication Date
ATE408151T1 true ATE408151T1 (de) 2008-09-15

Family

ID=8171311

Family Applications (1)

Application Number Title Priority Date Filing Date
AT01933773T ATE408151T1 (de) 2000-04-05 2001-03-29 Verfahren und prüfschnittstelle zum überprüfen von digitalschaltungen

Country Status (6)

Country Link
US (1) US6928597B2 (de)
EP (1) EP1272861B1 (de)
JP (1) JP2003530556A (de)
AT (1) ATE408151T1 (de)
DE (1) DE60135735D1 (de)
WO (1) WO2001077700A1 (de)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6656751B2 (en) * 2001-11-13 2003-12-02 International Business Machines Corporation Self test method and device for dynamic voltage screen functionality improvement
US7111208B2 (en) * 2002-10-02 2006-09-19 Broadcom Corporation On-chip standalone self-test system and method
US20040193986A1 (en) * 2003-03-31 2004-09-30 Canagasaby Karthisha S. On-die pattern generator for high speed serial interconnect built-in self test
US7139957B2 (en) * 2003-06-30 2006-11-21 Intel Corporation Automatic self test of an integrated circuit component via AC I/O loopback
WO2006061668A1 (en) * 2004-12-07 2006-06-15 Infineon Technologies Ag Test time reduction for multi-chip modules (mcm) and for system-in-packages (sip)
US7855969B2 (en) * 2005-05-24 2010-12-21 Lsi Corporation Selective test point for high speed SERDES cores in semiconductor design
JP4437986B2 (ja) * 2005-09-30 2010-03-24 富士通マイクロエレクトロニクス株式会社 半導体集積回路装置、インターフェース試験制御回路および試験方法
JP4422134B2 (ja) * 2006-09-29 2010-02-24 Ｏｋｉセミコンダクタ株式会社 Ｕｓｂテスト回路

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5787114A (en) 1996-01-17 1998-07-28 Lsi Logic Corporation Loop-back test system and method
US5790563A (en) * 1996-02-05 1998-08-04 Lsi Logic Corp. Self test of core with unpredictable latency
DE19832307C2 (de) * 1998-07-17 2000-09-21 Siemens Ag Integrierte Schaltung mit einer Selbsttesteinrichtung
US6493124B1 (en) * 1999-07-27 2002-12-10 Tellabs Operations, Inc. Looping back signals in optical switches
US6348811B1 (en) * 2000-06-28 2002-02-19 Intel Corporation Apparatus and methods for testing simultaneous bi-directional I/O circuits

Also Published As

Publication number Publication date
EP1272861B1 (de) 2008-09-10
WO2001077700A1 (en) 2001-10-18
US6928597B2 (en) 2005-08-09
EP1272861A1 (de) 2003-01-08
JP2003530556A (ja) 2003-10-14
US20020053056A1 (en) 2002-05-02
DE60135735D1 (de) 2008-10-23

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Legal Events

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