ATE407451T1 - Verankerung von dünnschichtmustern durch seitliche oxidation zum verhindern des entfeuchtungseffekts - Google Patents

Verankerung von dünnschichtmustern durch seitliche oxidation zum verhindern des entfeuchtungseffekts

Info

Publication number
ATE407451T1
ATE407451T1 AT05354026T AT05354026T ATE407451T1 AT E407451 T1 ATE407451 T1 AT E407451T1 AT 05354026 T AT05354026 T AT 05354026T AT 05354026 T AT05354026 T AT 05354026T AT E407451 T1 ATE407451 T1 AT E407451T1
Authority
AT
Austria
Prior art keywords
thin film
anchoring
prevent
film pattern
lateral oxidation
Prior art date
Application number
AT05354026T
Other languages
English (en)
Inventor
Jean-Charles Barbe
Beatrice Drevet
Maud Vinet
Carine Jahan
Original Assignee
Commissariat Energie Atomique
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Commissariat Energie Atomique filed Critical Commissariat Energie Atomique
Application granted granted Critical
Publication of ATE407451T1 publication Critical patent/ATE407451T1/de

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P54/00—Cutting or separating of wafers, substrates or parts of devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/03—Manufacture or treatment wherein the substrate comprises sapphire, e.g. silicon-on-sapphire [SOS]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H10P90/19—Preparing inhomogeneous wafers
    • H10P90/1904—Preparing vertically inhomogeneous wafers
    • H10P90/1906—Preparing SOI wafers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01—Manufacture or treatment
    • H10W10/011—Manufacture or treatment of isolation regions comprising dielectric materials
    • H10W10/012—Manufacture or treatment of isolation regions comprising dielectric materials using local oxidation of silicon [LOCOS]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01—Manufacture or treatment
    • H10W10/011—Manufacture or treatment of isolation regions comprising dielectric materials
    • H10W10/012—Manufacture or treatment of isolation regions comprising dielectric materials using local oxidation of silicon [LOCOS]
    • H10W10/0121—Manufacture or treatment of isolation regions comprising dielectric materials using local oxidation of silicon [LOCOS] in regions recessed from the surface, e.g. in trenches or grooves
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01—Manufacture or treatment
    • H10W10/061—Manufacture or treatment using SOI processes together with lateral isolation, e.g. combinations of SOI and shallow trench isolations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H10W10/13—Isolation regions comprising dielectric materials formed using local oxidation of silicon [LOCOS], e.g. sealed interface localised oxidation [SILO] or side-wall mask isolation [SWAMI]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H10W10/181—Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers

Landscapes

  • Formation Of Insulating Films (AREA)
  • Element Separation (AREA)
  • Thin Film Transistor (AREA)
  • Physical Vapour Deposition (AREA)
  • Compositions Of Oxide Ceramics (AREA)
  • Electroluminescent Light Sources (AREA)
  • Investigating Or Analyzing Materials By The Use Of Fluid Adsorption Or Reactions (AREA)
AT05354026T 2004-07-12 2005-07-04 Verankerung von dünnschichtmustern durch seitliche oxidation zum verhindern des entfeuchtungseffekts ATE407451T1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR0407751A FR2872958B1 (fr) 2004-07-12 2004-07-12 Procede de fabrication d'un film mince structure et film mince obtenu par un tel procede

Publications (1)

Publication Number Publication Date
ATE407451T1 true ATE407451T1 (de) 2008-09-15

Family

ID=34947933

Family Applications (1)

Application Number Title Priority Date Filing Date
AT05354026T ATE407451T1 (de) 2004-07-12 2005-07-04 Verankerung von dünnschichtmustern durch seitliche oxidation zum verhindern des entfeuchtungseffekts

Country Status (5)

Country Link
US (1) US7510919B2 (de)
EP (1) EP1617470B1 (de)
AT (1) ATE407451T1 (de)
DE (1) DE602005009438D1 (de)
FR (1) FR2872958B1 (de)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102540524B (zh) * 2010-12-30 2015-10-07 北京京东方光电科技有限公司 防止静电击穿的方法、阵列基板的制造方法和显示背板

Family Cites Families (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4753896A (en) * 1986-11-21 1988-06-28 Texas Instruments Incorporated Sidewall channel stop process
US4876217A (en) * 1988-03-24 1989-10-24 Motorola Inc. Method of forming semiconductor structure isolation regions
US5518949A (en) * 1995-07-18 1996-05-21 Winbond Electronics Corporation Electrical isolation method for devices made on SOI wafer
JP4027447B2 (ja) * 1996-04-24 2007-12-26 株式会社ルネサステクノロジ 半導体装置の製造方法
US6091077A (en) * 1996-10-22 2000-07-18 Matsushita Electric Industrial Co., Ltd. MIS SOI semiconductor device with RTD and/or HET
US6387741B1 (en) * 1999-06-03 2002-05-14 Asahi Kasei Microsystems Co., Ltd. Manufacturing a semiconductor device with isolated circuit-element formation layers of different thicknesses
US6248637B1 (en) * 1999-09-24 2001-06-19 Advanced Micro Devices, Inc. Process for manufacturing MOS Transistors having elevated source and drain regions
US6482707B1 (en) * 2000-03-21 2002-11-19 Micron Technology, Inc. Method of improving static refresh
US6881645B2 (en) * 2000-08-17 2005-04-19 Samsung Electronics Co., Ltd. Method of preventing semiconductor layers from bending and semiconductor device formed thereby
EP1220312A1 (de) * 2000-12-29 2002-07-03 STMicroelectronics S.r.l. Verfahren zur Integration eines Halbleiterbauelements auf einem SOI Substrat mit mindestens einer dielektrisch isolierten Wanne
JP5194328B2 (ja) * 2001-02-01 2013-05-08 ソニー株式会社 半導体装置及びその製造方法
US6521510B1 (en) * 2001-03-23 2003-02-18 Advanced Micro Devices, Inc. Method for shallow trench isolation with removal of strained island edges
JP2003086807A (ja) * 2001-09-10 2003-03-20 Oki Electric Ind Co Ltd 電界効果トランジスタの製造方法
US6624478B2 (en) * 2002-01-30 2003-09-23 International Business Machines Corporation High mobility transistors in SOI and method for forming
US6867462B2 (en) * 2002-08-09 2005-03-15 Matsushita Electric Industrial Co., Ltd. Semiconductor device using an SOI substrate and having a trench isolation and method for fabricating the same
DE10248723A1 (de) * 2002-10-18 2004-05-06 Infineon Technologies Ag Integrierte Schaltungsanordnung mit Kondensatoren und mit vorzugsweise planaren Transistoren und Herstellungsverfahren
JP4575002B2 (ja) * 2004-02-27 2010-11-04 Ｏｋｉセミコンダクタ株式会社 半導体装置の製造方法
US7202123B1 (en) * 2004-07-02 2007-04-10 Advanced Micro Devices, Inc. Mesa isolation technology for extremely thin silicon-on-insulator semiconductor devices

Also Published As

Publication number Publication date
US20060014333A1 (en) 2006-01-19
FR2872958B1 (fr) 2008-05-02
US7510919B2 (en) 2009-03-31
EP1617470A2 (de) 2006-01-18
DE602005009438D1 (de) 2008-10-16
EP1617470A3 (de) 2006-11-02
EP1617470B1 (de) 2008-09-03
FR2872958A1 (fr) 2006-01-13

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Legal Events

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